Editing Branch predictor (section)

===Neural branch prediction===
[[Machine learning]] for branch prediction using [[learning vector quantization|LVQ]] and [[multi-layer perceptron]]s, called "[[artificial neural network|neural]] branch prediction", was proposed by Lucian Vintan ([[Lucian Blaga University of Sibiu]]).<ref>{{cite conference |author-first=Lucian N. |author-last=Vintan |title=Towards a High Performance Neural Branch Predictor |book-title=Proceedings International Journal Conference on Neural Networks (IJCNN) |date=1999 |url=http://webspace.ulbsibiu.ro/lucian.vintan/html/USA.pdf |access-date=2010-12-02 |archive-date=2019-07-13 |archive-url=https://web.archive.org/web/20190713224752/http://webspace.ulbsibiu.ro/lucian.vintan/html/USA.pdf |url-status=dead}}</ref>
One year later he developed the perceptron branch predictor.<ref>{{cite journal |author-first=Lucian N. |author-last=Vintan |title=Towards a Powerful Dynamic Branch Predictor |journal=Romanian Journal of Information Science and Technology |volume=3 |issue=3 |pages=287–301 |issn=1453-8245 |publisher=Romanian Academy |location=Bucharest |date=2000 |url=http://webspace.ulbsibiu.ro/lucian.vintan/html/Rom_JIST.pdf}}</ref>
The neural branch predictor research was developed much further by Daniel Jimenez.<ref name="jimenez-perceptrons">{{cite conference |author-first1=D. A. |author-last1=Jimenez |author-first2=C. |author-last2=Lin |title=Dynamic Branch Prediction with Perceptrons |url=https://www.cs.utexas.edu/~lin/papers/hpca01.pdf |book-title=Proceedings of the 7th International Symposium on High Performance Computer Architecture (HPCA-7) |location=Monterrey, NL, Mexico |date=2001 |pages=197–296 |doi=10.1109/HPCA.2001.903263}}</ref>
In 2001,<ref name="jimenez-perceptrons"/> the first [[perceptron]] predictor was presented that was feasible to implement in hardware. The first commercial implementation of a perceptron branch predictor was in AMD's [[Piledriver (microarchitecture)|Piledriver microarchitecture]].<ref>{{cite web |url=http://www.anandtech.com/show/5831/amd-trinity-review-a10-4600m-a-new-hope |title=The AMD Trinity Review (A10-4600M): A New Hope |author-first=Jarred |author-last=Walton |date=2012-05-15 |website=[[AnandTech]]}}</ref>

The main advantage of the neural predictor is its ability to exploit long histories while requiring only linear resource growth. Classical predictors require exponential resource growth. Jimenez reports a global improvement of 5.7% over a McFarling-style hybrid predictor.<ref name="jimenez-micro-36">{{cite conference |url=http://www.microarch.org/micro36/html/pdf/jimenez-FastPath.pdf |author-first=Daniel A. |author-last=Jimenez |title=Fast Path-Based Neural Branch Prediction |doi=10.1109/MICRO.2003.1253199 |conference=The 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-36) |location=San Diego, USA |date=December 2003 |pages=243–252 |access-date=2018-04-08 |archive-date=2016-03-31 |archive-url=https://web.archive.org/web/20160331115200/http://www.microarch.org/micro36/html/pdf/jimenez-FastPath.pdf |url-status=dead }}</ref> He also used a gshare/perceptron overriding hybrid predictors.<ref name="jimenez-micro-36"/>

The main disadvantage of the perceptron predictor is its high latency. Even after taking advantage of high-speed arithmetic tricks, the computation latency is relatively high compared to the clock period of many modern microarchitectures. In order to reduce the prediction latency, Jimenez proposed in 2003 the ''fast-path neural predictor'', where the perceptron predictor chooses its weights according to the current branch's path, rather than according to the branch's PC. Many other researchers developed this concept (A. Seznec, M. Monchiero, D. Tarjan & K. Skadron, V. Desmet, Akkary et al., K. Aasaraai, Michael Black, etc.).{{citation needed|date=May 2013}}

Most of the state-of-the-art branch predictors are using a perceptron predictor (see Intel's "Championship Branch Prediction Competition"<ref>{{cite web |url=https://www.jilp.org/cbp2016/|title=Championship Branch Prediction}}</ref>). Intel already implements this idea in one of the [[IA-64]]'s simulators (2003).<ref>{{cite conference |author-first1=Edward |author-last1=Brekelbaum |author-first2=Jeff |author-last2=Rupley |author-first3=Chris |author-last3=Wilkerson |author-first4=Bryan |author-last4=Black |title=Hierarchical scheduling windows |doi=10.1109/MICRO.2002.1176236 |book-title=Proceedings of the 35th International Symposium on Microarchitecture |location=Istanbul, Turkey |date=December 2002}}</ref>

The [[AMD]] [[Ryzen]]<ref>{{cite web |url=https://www.pcgamesn.com/amd/amd-zen-release-date-specs-prices-rumours |title=AMD Ryzen reviews, news, performance, pricing, and availability |author-first=Dave |author-last=James |website=[[PCGamesN]]|date=2017-12-06}}</ref><ref>{{cite press release |url=https://www.amd.com/en/press-releases/amd-takes-computing-2016dec13 |title=AMD Takes Computing to a New Horizon with Ryzen™ Processors |publisher=[[AMD]] |access-date=2016-12-14}}</ref><ref>{{cite news |url=http://arstechnica.co.uk/gadgets/2016/12/amd-zen-performance-details-release-date/ |title=AMD's Zen CPU is now called Ryzen, and it might actually challenge Intel |newspaper=Ars Technica UK |access-date=2016-12-14}}</ref> multi-core processor's [[Infinity Control Fabric|Infinity Fabric]] and the [[Samsung]] [[Exynos]] processor include a perceptron-based neural branch predictor.