Editing CPU cache (section)

=={{Anchor|CACHE-MISS}}Cache miss==
A cache miss is a failed attempt to read or write a piece of data in the cache, which results in a main memory access with much longer latency. There are three kinds of cache misses: instruction read miss, data read miss, and data write miss.

''Cache read misses'' from an ''instruction'' cache generally cause the largest delay, because the processor, or at least the [[Simultaneous multithreading|thread of execution]], has to wait (stall) until the instruction is fetched from main memory. ''Cache read misses'' from a ''data'' cache usually cause a smaller delay, because instructions not dependent on the cache read can be issued and continue execution until the data are returned from main memory, and the dependent instructions can resume execution. ''Cache write misses'' to a ''data'' cache generally cause the shortest delay, because the write can be queued and there are few limitations on the execution of subsequent instructions; the processor can continue until the queue is full. For a detailed introduction to the types of misses, see [[cache performance measurement and metric]].