Editing Data General Nova (section)

====Memory reference instructions====
The Nova instruction set contained a pair of instructions that transferred memory contents to accumulators and vice versa, two transfer-of-control instructions, and two instructions that tested the contents of a memory location. All memory reference instructions contained an eight-bit address field, and a two-bit field that specified the mode of memory addressing. The four modes were:
* Mode 0 — absolute addressing. The contents of the address field of the instruction is zero-filled on the left and used as the target address.
* Mode 1 — relative addressing. The contents of the address field of the instruction is sign extended to the left and added to the current value of the program counter (which, by the time the instruction executes, points to the next instruction). The result is used as the target address.
* Mode 2 — indexed addressing. The contents of the address field of the instruction is sign extended to the left and added to the current value of accumulator 2. The result is used as the target address.
* Mode 3 — indexed addressing. The contents of the address field of the instruction is sign extended to the left and added to the current value of accumulator 3. The result is used as the target address.

Obviously, mode 0 was only capable of addressing the first 256 memory words, given the eight-bit address field. This portion of memory was referred to as "page zero". Page zero memory words were considered precious to Nova assembly language programmers because of the small number available; only page zero locations could be addressed from anywhere in the program without resorting to indexed addressing, which required tying up accumulator 2 or 3 to use as an index register. In assembly language, a {{code|.ZREL}} directive caused the assembler to place the instructions and data words that followed it in page zero; an {{code|.NREL}} directive placed the following instructions and data words in "normal" memory. Later Nova models added instructions with extended addressing fields, which overcame this difficulty (at a performance penalty).

The assembler computed relative offsets for mode 1 automatically, although it was also possible to write it explicitly in the source. If a memory reference instruction referenced a memory address in .NREL space but no mode specifier, mode 1 was assumed and the assembler calculated the offset between the current instruction and the referenced location, and placed this in the instruction's address field (provided that the resulting value fit into the 8-bit field).

The two load and store instructions were:
* {{code|LDA}} — load the contents of a memory location into the specified accumulator.
* {{code|STA}} — store the contents of the specified accumulator into a memory location.
Both of these instructions included an "indirect" bit. If this bit was set (done in assembly language by adding a {{code|@}} to the opcode), the contents of the target address were assumed to be a memory address itself, and that address would be referenced to do the load or store.

The two transfer-of-control instructions were:
* {{code|JMP}} — transfers control to the specified memory location
* {{code|JSR}} ("jump subroutine") — Does the same as the {{code|JMP}} instruction, but additionally loads the return address (the instruction following the {{code|JSR}} instruction in line) into accumulator 3 before jumping.
As in the case of the load and store instructions, the jump instructions contained an indirect bit, which likewise was specified in assembly using the {{code|@}} character. In the case of an indirect jump, the processor retrieved the contents of the target location, and used the value as the memory address to jump to. However, unlike the load and store instructions, if the indirect address had the most significant bit set, it would perform a further cycle of indirection. On the Nova series processors prior to the Nova 3, there was no limit on the number of indirection cycles; an indirect address that referenced itself would result in an infinite indirect addressing loop, with the instruction never completing. (This could be alarming to users, since when in this condition, pressing the STOP switch on the front panel did nothing. It was necessary to reset the machine to break the loop.)

The two memory test instructions were:
* {{code|ISZ}} — increment the memory location, and skip the next instruction if the result is zero.
* {{code|DSZ}} — decrement the memory location, and skip the next instruction if the result is zero.
As in the case of the load and store instructions, there was an indirect bit that would perform a single level of indirect addressing. These instructions were odd in that, on the Novas with magnetic core memory, the instruction was executed within the memory board itself. As was common at the time, the memory boards contained a "write-back" circuit to solve the destructive-read problem inherent to magnetic core memory. But the write-back mechanism also contained a mini arithmetic unit, which the processor used for several purposes. For the {{code|ISZ}} and {{code|DSZ}} instructions, the increment or decrement occurred between the memory location being read and the write-back; the CPU simply waited to be told if the result was zero or nonzero. These instructions were useful because they allowed a memory location to be used as a loop counter without tying up an accumulator, but they were slower than performing the equivalent arithmetic instructions.

Some examples of memory reference instructions:

{{sxhl|2=nasm|LDA 1,COUNT}}

Transfers the contents of the memory location labeled {{code|COUNT}} into accumulator 1. Assuming that {{code|COUNT}} is in .NREL space, this instruction is equivalent to

{{sxhl|2=nasm|LDA 1,1,(COUNT-(.+1))}}

where '.' represents the location of the LDA instruction.

{{sxhl|2=nasm|JSR@ 0,17}}

Jump indirect to the memory address specified by the contents of location 17, in page zero space, and deposit the return address in accumulator 3. This was the standard method for making an RDOS system call on early Nova models; the assembly language mnemonic {{code|.SYSTM}} translated to this.

{{sxhl|2=nasm|JMP 0,3}}

Jump to the memory location whose address is contained in accumulator 3. This was a common means of returning from a function or subroutine call, since the JSR instruction left the return address in accumulator 3.

{{sxhl|2=nasm|STA 0,3,-1}}

Store the contents of accumulator 0 in the location that is one less than the address contained in accumulator 3.

{{sxhl|2=nasm|DSZ COUNT}}

Decrement the value in the location labeled {{code|COUNT}}, and skip the next instruction if the result is zero. As in the case above, if {{code|COUNT}} is assumed to be in .NREL space, this is equivalent to:

{{sxhl|2=nasm|DSZ 1,(COUNT-(.+1))}}