Editing Flash memory (section)

====Cost====
[[File:3D NAND minimum cost example.png|thumb|right|300px|'''Minimum bit cost of 3D NAND from non-vertical sidewall.''' The top opening widens with more layers, counteracting the increase in bit density.]]
The wafer cost of a 3D NAND is comparable with scaled down (32&nbsp;nm or less) planar NAND flash.<ref>{{cite web|url=https://www.linkedin.com/pulse/toshibas-cost-model-3d-nand-frederick-chen|title=Toshiba's Cost Model for 3D NAND|website=www.linkedin.com}}</ref> However, with planar NAND scaling stopping at 16&nbsp;nm, the cost per bit reduction can continue by 3D NAND starting with 16 layers. However, due to the non-vertical sidewall of the hole etched through the layers; even a slight deviation leads to a minimum bit cost, i.e., minimum equivalent design rule (or maximum density), for a given number of layers; this minimum bit cost layer number decreases for smaller hole diameter.<ref>{{cite web |title=Calculating the Maximum Density and Equivalent 2D Design Rule of 3D NAND Flash |url=https://www.linkedin.com/pulse/calculating-maximum-density-equivalent-2d-design-rule-frederick-chen |website=linkedin.com |access-date=1 June 2022}}; {{cite web |url=https://semiwiki.com/lithography/296121-calculating-the-maximum-density-and-equivalent-2d-design-rule-of-3d-nand-flash/ |title=Calculating the Maximum Density and Equivalent 2D Design Rule of 3D NAND Flash |website=semwiki.com |access-date=1 June 2022}}</ref>