Editing Dynamic random-access memory (section)

==Security==

===Data remanence===
{{Main|Data remanence}}

Although dynamic memory is only specified and ''guaranteed'' to retain its contents when supplied with power and refreshed every short period of time (often {{nowrap|64 ms}}), the memory cell [[capacitor]]s often retain their values for significantly longer time, particularly at low temperatures.<ref name=citp /> Under some conditions most of the data in DRAM can be recovered even if it has not been refreshed for several minutes.<ref name="Scheick1">{{Cite journal|last1=Scheick|first1=Leif Z.|last2=Guertin|first2=Steven M.|last3=Swift|first3=Gary M.|title=Analysis of radiation effects on individual DRAM cells|journal=IEEE Transactions on Nuclear Science|volume=47|issue=6|pages=2534–2538|date=December 2000|issn=0018-9499|doi=10.1109/23.903804|bibcode=2000ITNS...47.2534S}}</ref>

This property can be used to circumvent security and recover data stored in the main memory that is assumed to be destroyed at power-down. The computer could be quickly rebooted, and the contents of the main memory read out; or by removing a computer's memory modules, cooling them to prolong data remanence, then transferring them to a different computer to be read out. Such an attack was demonstrated to circumvent popular disk encryption systems, such as the [[Open-source software|open source]] [[TrueCrypt]], Microsoft's [[BitLocker Drive Encryption]], and [[Apple Inc.|Apple]]'s [[FileVault]].<ref name=citp>{{cite web|title=Center for Information Technology Policy » Lest We Remember: Cold Boot Attacks on Encryption Keys |url=http://citp.princeton.edu/memory/ |url-status=dead |archive-url=https://web.archive.org/web/20110722182409/http://citp.princeton.edu/memory/ |archive-date=July 22, 2011 }} 080222 citp.princeton.edu</ref> This type of attack against a computer is often called a [[cold boot attack]].

===Memory corruption===
{{See also|#Operations to read a data bit from a DRAM storage cell}}

Dynamic memory, by definition, requires periodic refresh. Furthermore, reading dynamic memory is a destructive operation, requiring a recharge of the storage cells in the row that has been read. If these processes are imperfect, a read operation can cause [[soft error]]s. In particular, there is a risk that some charge can leak between nearby cells, causing the refresh or read of one row to cause a ''disturbance error'' in an adjacent or even nearby row. The awareness of disturbance errors dates back to the first commercially available DRAM in the early 1970s (the [[Intel 1103]]). Despite the mitigation techniques employed by manufacturers, commercial researchers proved in a 2014 analysis that commercially available [[DDR3]] DRAM chips manufactured in 2012 and 2013 are susceptible to disturbance errors.<ref>{{cite web | url = http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_kim_talk_isca14.pdf | title = Flipping Bits in Memory Without Accessing Them: DRAM Disturbance Errors | date = June 24, 2014 | access-date = March 10, 2015 | author1 = Yoongu Kim | author2 = Ross Daly | author3 = Jeremie Kim | author4 = Chris Fallin | author5 = Ji Hye Lee | author6 = Donghyuk Lee | author7 = Chris Wilkerson | author8 = Konrad Lai | author9 = Onur Mutlu | website = ece.cmu.edu | url-status = live | archive-url = https://web.archive.org/web/20150326080426/http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_kim_talk_isca14.pdf | archive-date = 2015-03-26 }}</ref> The associated side effect that led to observed bit flips has been dubbed ''[[row hammer]]''.