Editing List of interface bit rates (section)

===Graphics processing units' RAM===
RAM memory modules are also utilised by [[graphics processing unit]]s; however, memory modules for those differ somewhat from standard computer memory, particularly with lower power requirements, and are specialised to serve GPUs: for example, [[GDDR3]] was fundamentally based on [[DDR2 SDRAM|DDR2]]. Every graphics memory chip is directly connected to the GPU (point-to-point). The total GPU memory bus width varies with the number of memory chips and the number of lanes per chip. For example, GDDR5 specifies either 16 or 32 lanes per ''device'' (chip), while GDDR5X specifies 64 lanes per chip. Over the years, bus widths rose from 64-bit to 512-bit and beyond: e.g. [[High Bandwidth Memory|HBM]] is 1024 bits wide.<ref>[[Comparison of AMD graphics processing units]]</ref>
Because of this variability, graphics memory speeds are sometimes compared per pin. For direct comparison to the values for 64-bit modules shown above, video RAM is compared here in 64-lane lots, corresponding to two chips for those devices with 32-bit widths.
In 2012, high-end GPUs used 8 or even 12 chips with 32 lanes each, for a total memory bus width of 256 or 384 bits. Combined with a transfer rate per pin of 5&nbsp;GT/s or more, such cards could reach 240&nbsp;GB/s or more.

RAM frequencies used for a given chip technology vary greatly. Where single values are given below, they are examples from high-end cards.<ref>[[Comparison of Nvidia graphics processing units]]</ref> Since many cards have more than one pair of chips, the total bandwidth is correspondingly higher. For example, high-end cards often have eight chips, each 32 bits wide, so the total bandwidth for such cards is four times the value given below.

{|class="wikitable sortable"
|-
! Chip type
! Module type !! Memory clock !! Transfers/s !! colspan=2 |Bandwidth
|-
|[[DDR SDRAM|DDR]]
|64 lanes
|align=right| {{val|350|ul=MHz}}
|align=right| {{val|0.7|ul=GT/s}}
|align=right| {{val|44.8|u=Gbit/s}}
|align=right| {{val|5.6|u=GB/s}} <!-- GF 6800 -->
|-
|[[DDR2 SDRAM|DDR2]]
|64 lanes
|align=right| {{val|250|u=MHz}}
|align=right| {{val|1|u=GT/s}}
|align=right| {{val|64|u=Gbit/s}}
|align=right| {{val|8|u=GB/s}} <!-- GF 5800 Ultra -->
|-
|[[GDDR3]]
|64 lanes
|align=right| {{val|625|u=MHz}}
|align=right| {{val|2.5|u=GT/s}}
|align=right| {{val|159|u=Gbit/s}}
|align=right| {{val|19.9|u=GB/s}} <!-- GF GTX 285 -->
|-
|[[GDDR4]]
|64 lanes
|align=right| {{val|275|u=MHz}}
|align=right| {{val|2.2|u=GT/s}}
|align=right| {{val|140.8|u=Gbit/s}}
|align=right| {{val|17.6|u=GB/s}} <!-- Rd HD 4670 -->
|-
|[[GDDR5]]<ref>{{cite web |url=https://www.jedec.org/standards-documents/docs/jesd212c |publisher=JEDEC |title=GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD JESD212C |date=2016-02-01 |access-date=2016-08-10}}</ref>
| 64 lanes
|align=right| {{val|625|-|1125|u=MHz}}
|align=right| {{val|5|-|9|u=GT/s}}
|align=right| {{val|320|-|576|u=Gbit/s}}
|align=right| {{val|40|-|72|u=GB/s}}
|-
|[[GDDR5X]]<ref>{{cite web |url=https://www.jedec.org/standards-documents/docs/jesd232a |publisher=JEDEC |title=GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD JESD232 |date=2015-11-01 |access-date=2016-08-10}}</ref>
|64 lanes
|align=right| {{val|625|-|875|u=MHz}}
|align=right| {{val|10|-|12|u=GT/s}}
|align=right| {{val|640|-|768|u=Gbit/s}}
|align=right| {{val|80|-|96|u=GB/s}}
|-
|[[GDDR6]]
|64 lanes
|align=right| {{val|875|–|1125|u=MHz}}
|align=right| {{val|14|-|18|u=GT/s}}
|align=right| {{val|896|–|1152|u=Gbit/s}}
|align=right| {{val|112|–|144|u=GB/s}}
|-
|[[GDDR6X]]<ref>{{cite web |title=Doubling I/O Performance with PAM4 - Micron Innovates GDDR6X to Accelerate Graphics Memory |url=https://media-www.micron.com/-/media/client/global/documents/products/technical-marketing-brief/gddr6x_pam4_2x_speed_tech_brief |website=Micron |access-date=11 September 2020}}</ref>
|64 lanes
|align=right| {{val|594|–|656|u=MHz}}
|align=right| {{val|19|-|21|u=GT/s}}
|align=right| {{val|1216|–|1344|u=Gbit/s}}
|align=right| {{val|152|–|168|u=GB/s}}
|-
|[[High Bandwidth Memory|HBM]]<ref name="HBM2_anand">{{cite news |last1=Shilov |first1=Anton |title=JEDEC Publishes HBM2 Specification |url=https://www.anandtech.com/show/9969/jedec-publishes-hbm2-specification |access-date=16 May 2017 |publisher=Anandtech |date=20 January 2016}}</ref>
|1024 lanes (8 channels @ 128 lanes ea)
|align=right| {{val|500|u=MHz}}
|align=right| {{val|1|u=GT/s}}
|align=right| {{val|1024|u=Gbit/s}}
|align=right| {{val|128|u=GB/s}}
|-
|[[High Bandwidth Memory#HBM 2|HBM2]]<ref name="HBM2_anand" />
|1024 lanes (8 channels @ 128 lanes ea)
|align=right| {{val|1000|u=MHz}}
|align=right| {{val|2|u=GT/s}}
|align=right| {{val|2048|u=Gbit/s}}
|align=right| {{val|256|u=GB/s}}
|-
|[[High Bandwidth Memory#HBM2E|HBM2e]]<ref name="hbm2e_toms">{{cite news |last1=Harding |first1=Scharon |title=What Are HBM, HBM2 and HBM2E? A Basic Definition|url=https://www.tomshardware.com/reviews/glossary-hbm-hbm2-high-bandwidth-memory-definition,5889.html |access-date=4 May 2022 |publisher=Tom's Hardware|date=15 April 2021}}</ref>
|1024 lanes (8 channels @ 128 lanes ea)
|align=right| {{val|1800|u=MHz}}
|align=right| {{val|3.6|u=GT/s}}
|align=right| {{val|3686.4|u=Gbit/s}}
|align=right| {{val|460.8|u=GB/s}}
|-
|[[High Bandwidth Memory#HBM 3|HBM3]]<ref name="hbm2e_toms" /><ref name="hbm3_next">{{cite news |last1=Prickett Morgan |first1=Timothy |title=The HBM3 roadmap is just getting started|url=https://www.nextplatform.com/2022/04/06/the-hbm3-roadmap-is-just-getting-started/ |access-date=4 May 2022 |publisher=TheNextPlatform |date=6 April 2022}}</ref>
|1024 lanes (16 channels @ 64 lanes ea)
|align=right| {{val|3200|u=MHz}}
|align=right| {{val|6.4|u=GT/s}}
|align=right|  {{val|6553.6|u=Gbit/s}}
|align=right| {{val|819.2|u=GB/s}}
|-
|[[High Bandwidth Memory#HBM3E|HBM3E]]<ref name="hbm2e_toms" /><ref name="hbm3_next">{{cite news |last1=Prickett Morgan |first1=Timothy |title=The HBM3 roadmap is just getting started|url=https://www.nextplatform.com/2022/04/06/the-hbm3-roadmap-is-just-getting-started/ |access-date=4 May 2022 |publisher=TheNextPlatform |date=6 April 2022}}</ref>
|1024 lanes (16 channels @ 64 lanes ea)
|align=right| up to {{val|4900|u=MHz}}
|align=right| up to {{val|9.8|u=GT/s}}
|align=right| up to {{val|10035|u=Gbit/s}}
|align=right| up to {{val|1.25|u=TB/s}}
|-
| [[Hybrid Memory Cube|HMC]]
|128 lanes (8 links @ 16 lanes ea)
|align=right| (internal)
|align=right| {{val|10|u=GT/s}}
|align=right| {{val|2560|u=Gbit/s}}
|align=right| {{val|320|u=GB/s}}
|-
| [[Hybrid Memory Cube|HMC2]]
|64 lanes (4 links @ 16 lanes ea)
|align=right| (internal)
|align=right| {{val|30|u=GT/s}}
|align=right| {{val|3840|u=Gbit/s}}
|align=right| {{val|480|u=GB/s}}
|}