Editing MOSFET (section)

=== Gate material ===
The primary criterion for the gate material is that it is a good [[conductor (material)|conductor]]. Highly doped [[polycrystalline silicon]] is an acceptable but certainly not ideal conductor, and also suffers from some more technical deficiencies in its role as the standard gate material. Nevertheless, there are several reasons favoring use of polysilicon:

# The [[threshold voltage]] (and consequently the drain to source on-current) is modified by the [[work function]] difference between the gate material and channel material. Because polysilicon is a semiconductor, its work function can be modulated by adjusting the type and level of doping. Furthermore, because polysilicon has the same [[bandgap]] as the underlying silicon channel, it is quite straightforward to tune the work function to achieve low threshold voltages for both NMOS and PMOS devices. By contrast, the work functions of metals are not easily modulated, so tuning the [[work function]] to obtain [[low threshold voltage]]s (LVT) becomes a significant challenge. Additionally, obtaining low-threshold devices on both PMOS and NMOS devices sometimes requires the use of different metals for each device type. 
# The silicon-SiO<sub>2</sub> interface has been well studied and is known to have relatively few defects. By contrast many metal-insulator interfaces contain significant levels of defects which can lead to [[Fermi level pinning]], charging, or other phenomena that ultimately degrade device performance.
# In the MOSFET [[IC fabrication]] process, it is preferable to deposit the gate material prior to certain high-temperature steps in order to make better-performing transistors. Such high temperature steps would melt some metals, limiting the types of metal that can be used in a metal-gate-based process.

While polysilicon gates have been the de facto standard for the last twenty years, they do have some disadvantages which have led to their likely future replacement by metal gates. These disadvantages include:

* Polysilicon is not a great conductor (approximately 1000 times more resistive than metals) which reduces the signal propagation speed through the material. The resistivity can be lowered by increasing the level of doping, but even highly doped polysilicon is not as conductive as most metals. To improve conductivity further, sometimes a high-temperature metal such as [[tungsten]], [[titanium]], [[cobalt]], and more recently [[nickel]] is alloyed with the top layers of the polysilicon. Such a blended material is called [[silicide]]. The silicide-polysilicon combination has better electrical properties than polysilicon alone and still does not melt in subsequent processing. Also the threshold voltage is not significantly higher than with polysilicon alone, because the silicide material is not near the channel. The process in which silicide is formed on both the gate electrode and the source and drain regions is sometimes called [[salicide]], self-aligned silicide.
* When the transistors are extremely scaled down, it is necessary to make the gate dielectric layer very thin, around 1&nbsp;nm in state-of-the-art technologies. A phenomenon observed here is the so-called [[poly depletion]], where a depletion layer is formed in the gate polysilicon layer next to the gate dielectric when the transistor is in the inversion. To avoid this problem, a metal gate is desired. A variety of metal gates such as [[tantalum]], tungsten, [[tantalum nitride]], and [[titanium nitride]] are used, usually in conjunction with [[high-κ dielectric]]s. An alternative is to use fully silicided polysilicon gates, a process known as [[FUSI]].

Present high performance CPUs use metal gate technology, together with [[high-κ dielectric]]s, a combination known as ''high-κ, metal gate'' (HKMG). The disadvantages of metal gates are overcome by a few techniques:<ref>{{cite web|archive-url=https://web.archive.org/web/20100919004000/http://www.revera.com/VeraFlex/hkmg_approaches.htm|archive-date=19 September 2010|url= http://www.revera.com/VeraFlex/hkmg_approaches.htm|title=ReVera's FinFET Control|website=revera.com}}</ref>

# The threshold voltage is tuned by including a thin "work function metal" layer between the high-κ dielectric and the main metal. This layer is thin enough that the total work function of the gate is influenced by both the main metal and thin metal work functions (either due to alloying during annealing, or simply due to the incomplete screening by the thin metal). The threshold voltage thus can be tuned by the thickness of the thin metal layer.
# High-κ dielectrics are now well studied, and their defects are understood.
# HKMG processes exist that do not require the metals to experience high temperature anneals; other processes select metals that can survive the annealing step.