Editing PCI Express (section)

== History and revisions ==
While in early development, PCIe was initially referred to as ''HSI'' (for ''High Speed Interconnect''), and underwent a name change to ''3GIO'' (for ''3rd Generation I/O'') before finally settling on its [[PCI-SIG]] name ''PCI Express''. A technical working group named the ''Arapaho Work Group'' (AWG) drew up the standard. For initial drafts, the AWG consisted only of Intel engineers; subsequently, the AWG expanded to include industry partners.

Since, PCIe has undergone several large and smaller revisions, improving on performance and other features.

=== Comparison table ===
{| class="wikitable" style="text-align:right"
|+ PCI Express link performance<ref name="faq4" /><ref name="faq3" />
|- style="line-height:120%"
! scope="col" rowspan=2 | Version
! scope="col" rowspan=2 | Intro-<br />duced
! scope="col" rowspan=2 colspan=2 | Line code
! scope="col" rowspan=2 | Transfer rate<br />(per lane){{Efn-lr|name="both-directions"|In each direction (each lane is a dual simplex channel).}}{{Efn-lr|name="transfer-rate"|Transfer rate refers to the encoded serial bit rate; 2.5 GT/s means 2.5&nbsp;Gbit/s serial data rate.}}
! scope="col" colspan=5 | Throughput{{Efn-lr|name="both-directions"}}{{Efn-lr|name="throughput"|Throughput indicates the usable bandwidth (i.e. only including the payload, not the 8b/10b, 128b/130b, or 242B/256B encoding overhead). The PCIe 1.0 transfer rate of 2.5&nbsp;GT/s per lane means a 2.5&nbsp;Gbit/s serial bit rate; after applying a 8b/10b encoding, this corresponds to a useful throughput of 2.0&nbsp;Gbit/s &#61; 250&nbsp;MB/s.}}
|-
! scope="col" | ×1
! scope="col" | ×2
! scope="col" | ×4
! scope="col" | ×8
! scope="col" | ×16
|-
! scope="row" | 1.0
| 2003
| rowspan=5 | [[Non-return-to-zero|NRZ]]
| rowspan=2 | [[8b/10b]]
| {{Nowrap|2.5 [[GT/s]]}}
| {{Nowrap|0.250 [[GB/s]]}}
| {{COther|{{Nowrap|0.500 GB/s}}|align=right}}
| {{Nowrap|1.000 GB/s}}
| {{COther|{{Nowrap|2.000 GB/s}}|align=right}}
| {{Nowrap|4.000 GB/s}}
|-
! scope="row" | 2.0
| 2007
| {{Nowrap|5.0 GT/s}}
| {{COther|{{Nowrap|0.500 GB/s}}|align=right}}
| {{Nowrap|1.000 GB/s}}
| {{COther|{{Nowrap|2.000 GB/s}}|align=right}}
| {{Nowrap|4.000 GB/s}}
| {{CNone|{{Nowrap|8.000 GB/s}}|align=right}}
|-
! scope="row" | 3.0
| 2010
| rowspan=3 | [[128b/130b]]
| {{Nowrap|8.0 GT/s}}
| {{Nowrap|0.985 GB/s}}
| {{COther|{{Nowrap|1.969 GB/s}}|align=right}}
| {{Nowrap|3.938 GB/s}}
| {{CNone|{{Nowrap|{{0|0}}7.877 GB/s}}|align=right}}
| {{Nowrap|15.754 GB/s}}
|-
! scope="row" | 4.0
| 2017
| {{Nowrap|16.0 GT/s}}
| {{COther|{{Nowrap|1.969 GB/s}}|align=right}}
| {{Nowrap|3.938 GB/s}}
| {{CNone|{{Nowrap|{{0|0}}7.877 GB/s}}|align=right}}
| {{Nowrap|15.754 GB/s}}
| {{CNone|{{Nowrap|{{0|0}}31.508 GB/s}}|align=right}}
|-
! scope="row" | 5.0
| 2019
| {{Nowrap|32.0 GT/s}}
| {{Nowrap|3.938 GB/s}}
| {{CNone|{{Nowrap|{{0|0}}7.877 GB/s}}|align=right}}
| {{Nowrap|15.754 GB/s}}
| {{CNone|{{Nowrap|31.508 GB/s}}|align=right}}
| {{Nowrap|63.015 GB/s}}
|-
! scope="row" | 6.0 
| 2022
| rowspan=2 | {{Nowrap|[[PAM-4]]}}<br />[[Forward error correction|FEC]]
| rowspan=2 | 1b/1b<br />242B/256B [[Flit (computer networking)|FLIT]]
| {{Nowrap|64.0 GT/s}}<br />{{Nowrap|32.0 G[[Baud|Bd]]}}
| {{CNone|{{Nowrap|7.563 GB/s}}|align=right}}
| {{Nowrap|15.125 GB/s}}
| {{CNone|{{Nowrap|30.250 GB/s}}|align=right}}
| {{Nowrap|60.500 GB/s}}
| {{CNone|{{Nowrap|121.000 GB/s}}|align=right}}
|-
! scope="row" | 7.0 
| 2025<br />(planned)
| {{Nowrap|128.0 GT/s}}<br />{{Nowrap|64.0 GBd}}
| {{Nowrap|15.125 GB/s}}
| {{CNone|{{Nowrap|30.250 GB/s}}|align=right}}
| {{Nowrap|60.500 GB/s}}
| {{CNone|{{Nowrap|121.000 GB/s}}|align=right}}
| {{Nowrap|242.000 GB/s}}
|}

; Notes
{{Notelist-lr}}

=== PCI Express 1.0a <span class="anchor" id="1.0"></span><span class="anchor" id="1.0a"></span> ===
In 2003, PCI-SIG introduced PCIe 1.0a, with a per-lane data rate of 250&nbsp;MB/s and a [[transfer (computing)|transfer rate]] of 2.5 gigatransfers per second (GT/s).

Transfer rate is expressed in transfers per second instead of bits per second because the number of transfers includes the overhead bits, which do not provide additional throughput;<ref name="HroAC" /> PCIe 1.x uses an [[8b/10b encoding]] scheme, resulting in a 20% (=&nbsp;2/10) overhead on the raw channel bandwidth.<ref name="tfQxK" /> So in the PCIe terminology, transfer rate refers to the encoded bit rate: 2.5&nbsp;GT/s is 2.5&nbsp;Gbit/s on the encoded serial link. This corresponds to 2.0&nbsp;Gbit/s of pre-coded data or 250&nbsp;MB/s, which is referred to as throughput in PCIe.

==== PCI Express 1.1 <span class="anchor" id="1.1"></span> ====
In 2005, PCI-SIG<ref name="n9qGs" /> introduced PCIe 1.1. This updated specification includes clarifications and several improvements, but is fully compatible with PCI Express 1.0a. No changes were made to the data rate.

=== PCI Express 2.0 <span class="anchor" id="2.0"></span> ===
[[File:Rosewill-USB3-PCI-Express-Card.jpg|thumb|A PCI Express&nbsp;2.0 x1 expansion card that provides USB&nbsp;3.0 connectivity{{Efn|The card's [[Serial ATA#Standard connector|Serial ATA power connector]] is present because the USB&nbsp;3.0 ports require more power than the PCI Express bus can supply. More often, a [[Molex connector#Disk drive|4-pin Molex power connector]] is used.}}]]

[[PCI-SIG]] announced the availability of the PCI Express Base 2.0 specification on 15 January 2007.<ref name="PCIExpressPressRelease" /> The PCIe 2.0 standard doubles the transfer rate compared with PCIe 1.0 to 5{{nbsp}}GT/s and the per-lane throughput rises from 250&nbsp;MB/s to 500&nbsp;MB/s. Consequently, a 16-lane PCIe connector (x16) can support an aggregate throughput of up to 8&nbsp;GB/s.

PCIe 2.0 motherboard slots are fully [[backward compatible]] with PCIe v1.x cards. PCIe 2.0 cards are also generally backward compatible with PCIe 1.x motherboards, using the available bandwidth of PCI Express 1.1. Overall, graphic cards or motherboards designed for v2.0 work, with the other being v1.1 or v1.0a.

The PCI-SIG also said that PCIe 2.0 features improvements to the point-to-point data transfer protocol and its software architecture.<ref name="UaYlc" />

[[Intel Corporation|Intel]]'s first PCIe 2.0 capable chipset was the [[G35 (chipset)|X38]] and boards began to ship from various vendors ([[Universal abit|Abit]], [[Asus]], [[Gigabyte Technology|Gigabyte]]) as of 21 October 2007.<ref name="wHHTf" /> AMD started supporting PCIe 2.0 with its [[AMD 700 chipset series]] and nVidia started with the [[nForce 700|MCP72]].<ref name="gL2GQ" /> All of Intel's prior chipsets, including the [[Intel P35]] chipset, supported PCIe 1.1 or 1.0a.<ref name="mUQKD" />

Like 1.x, PCIe 2.0 uses an [[8b/10b encoding]] scheme, therefore delivering, per-lane, an effective 4&nbsp;Gbit/s max. transfer rate from its 5&nbsp;GT/s raw data rate.

==== PCI Express 2.1 <span class="anchor" id="2.1"></span> ====
PCI Express 2.1 (with its specification dated 4 March 2009) supports a large proportion of the management, support, and troubleshooting systems planned for full implementation in PCI Express 3.0. However, the speed is the same as PCI Express 2.0. The increase in power from the slot breaks backward compatibility between PCI Express 2.1 cards and some older motherboards with 1.0/1.0a, but most motherboards with PCI Express 1.1 connectors are provided with a BIOS update by their manufacturers through utilities to support backward compatibility of cards with PCIe 2.1.

=== PCI Express 3.0 <span class="anchor" id="3.0"></span> ===
PCI Express 3.0 Base specification revision 3.0 was made available in November 2010, after multiple delays. In August 2007, PCI-SIG announced that PCI Express 3.0 would carry a bit rate of 8 [[gigatransfer]]s per second (GT/s), and that it would be backward compatible with existing PCI Express implementations. At that time, it was also announced that the final specification for PCI Express 3.0 would be delayed until Q2 2010.<ref name="cVjNG" /> New features for the PCI Express 3.0 specification included a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, [[phase-locked loop|PLL]] improvements, clock data recovery, and channel enhancements of currently supported topologies.<ref name="extrmetech" />

Following a six-month technical analysis of the feasibility of scaling the PCI Express interconnect bandwidth, PCI-SIG's analysis found that 8 gigatransfers per second could be manufactured in mainstream silicon process technology, and deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) with the PCI Express protocol stack.

PCI Express&nbsp;3.0 upgraded the [[encoding scheme]] to 128b/130b from the previous [[8b/10b encoding]], reducing the bandwidth overhead from 20% of  PCI Express&nbsp;2.0 to approximately 1.54% (=&nbsp;2/130). PCI Express 3.0's 8&nbsp;GT/s bit rate effectively delivers 985&nbsp;MB/s per lane, nearly doubling the lane bandwidth relative to PCI Express 2.0.<ref name="faq3" />

On 18 November 2010, the PCI Special Interest Group officially published the finalized PCI Express 3.0 specification to its members to build devices based on this new version of PCI Express.<ref name="ajVA3" />

==== PCI Express 3.1 <span class="anchor" id="3.1"></span> ====
In September 2013, PCI Express&nbsp;3.1 specification was announced for release in late 2013 or early 2014, consolidating various improvements to the published PCI Express&nbsp;3.0 specification in three areas: power management, performance and functionality.<ref name="PoRghEr" /><ref name="5lvIH" /> It was released in November 2014.<ref name="9EIkz" />

=== PCI Express 4.0 <span class="anchor" id="4.0"></span> ===
On 29 November 2011, PCI-SIG preliminarily announced PCI Express 4.0,<ref name="W466M" /> providing a 16&nbsp;GT/s bit rate that doubles the bandwidth provided by PCI Express 3.0 to 31.5&nbsp;GB/s in each direction for a 16-lane configuration, while maintaining backward and [[forward compatibility]] in both software support and used mechanical interface.<ref name="QNZsy" /> PCI Express 4.0 specs also bring OCuLink-2, an alternative to [[Thunderbolt (interface)|Thunderbolt]]. OCuLink version 2 has up to 16&nbsp;GT/s (16{{nbsp}}GB/s total for x8 lanes),<ref name="OCuLink2" /> while the maximum bandwidth of a Thunderbolt 3 link is 5{{nbsp}}GB/s.

In June 2016 Cadence, PLDA and Synopsys demonstrated PCIe 4.0 physical-layer, controller, switch and other IP blocks at the PCI SIG’s annual developer’s conference.<ref name="EE_4+5" />
 
[[Mellanox Technologies]] announced the first 100{{nbsp}}Gbit/s network adapter with PCIe 4.0 on 15 June 2016,<ref name="FZ4hQ" /> and the first 200{{nbsp}}Gbit/s network adapter with PCIe 4.0 on 10 November 2016.<ref name="zovf4" />

In August 2016, [[Synopsys]] presented a test setup with FPGA clocking a lane to PCIe 4.0 speeds at the [[Intel Developer Forum]]. Their IP has been licensed to several firms planning to present their chips and products at the end of 2016.<ref name="heise_idf_2016" />

On the IEEE Hot Chips Symposium in August 2016 [[IBM]] announced the first CPU with PCIe 4.0 support, [[POWER9]].<ref name="HC28-IBM-Power9">{{Cite web|url=https://old.hotchips.org/wp-content/uploads/hc_archives/hc28/HC28.23-Tuesday-Epub/HC28.23.90-High-Perform-Epub/HC28.23.921-.POWER9-Thompto-IBM-final.pdf|title=Brian Thompto, POWER9 Processor for the Cognitive Era}}</ref><ref name="IEEE-Power9">[https://ieeexplore.ieee.org/xpl/conhome/7932734/proceeding 2016 IEEE Hot Chips 28 Symposium (HCS), 21–23 Aug. 2016]</ref>

PCI-SIG officially announced the release of the final PCI Express 4.0 specification on 8 June 2017.<ref name="TR_pcie4" /> The spec includes improvements in flexibility, scalability, and lower-power.

On 5 December 2017 IBM announced the first system with PCIe 4.0 slots, Power AC922.<ref name="2HOSh" /><ref name="IBM-ZG17-0147">{{Cite web|url=https://www.ibm.com/docs/en/announcements/archive/ENUSZG17-0147|title=IBM Power System AC922 (8335-GTG) server helps you to harness breakthrough accelerated AI, HPDA, and HPC performance for faster time to insight|date=2017-12-05|access-date=2025-04-25|website=www.ibm.com|archive-url=https://web.archive.org/web/20240627011358/https://www.ibm.com/docs/en/announcements/archive/ENUSZG17-0147|archive-date=2024-06-27|url-status=live}}</ref>

NETINT Technologies introduced the first [[NVM Express|NVMe]] SSD based on PCIe 4.0 on 17 July 2018, ahead of Flash Memory Summit 2018<ref name="ChNhD" />

[[Advanced Micro Devices|AMD]] announced on 9 January 2019 its upcoming [[Zen 2]]-based processors and X570 chipset would support PCIe 4.0.<ref name="Akskd" /> AMD had hoped to enable partial support for older chipsets, but instability caused by motherboard traces not conforming to PCIe 4.0 specifications made that impossible.<ref name="KDBMK" /><ref name="CAY71" />

Intel released their first mobile CPUs with PCI Express 4.0 support in mid-2020, as a part of the [[Tiger Lake (microprocessor)|Tiger Lake]] microarchitecture.<ref name="C02lC" />

=== PCI Express 5.0 <span class="anchor" id="5.0"></span> ===
[[File:Detailaufnahme des ASRock TRX50 WS 20240406 HOF1835-HDR RAW-Export 000185.png|thumb|Three PCIe 5.0 x16 (first and third slots at x16, fourth slot at x8 throughput) and two PCIe 4.0 x16 slots (second slot at x4, fifth slot at x8 throughput) on a 2023 workstation mainboard.]]
In June 2017, PCI-SIG announced the PCI Express 5.0 preliminary specification.<ref name="TR_pcie4" /> Bandwidth was expected to increase to 32{{nbsp}}GT/s, yielding 63{{nbsp}}GB/s<!-- 32 GT/s × 16 × 128/130 / 8 = 63,015,384,615 B/s --> in each direction in a 16-lane configuration. The draft spec was expected to be standardized in 2019.{{citation needed|date=July 2019}} Initially, {{Nowrap|25.0 GT/s}} was also considered for technical feasibility.

On 7 June 2017 at PCI-SIG DevCon, Synopsys recorded the first demonstration of PCI Express 5.0 at 32&nbsp;GT/s.<ref name="Syn50" />

On 31 May 2018, PLDA announced the availability of their XpressRICH5 PCIe 5.0 Controller IP based on draft 0.7 of the PCIe 5.0 specification on the same day.<ref name="n6z9y" /><ref name="9OVm8" />

On 10 December 2018, the PCI SIG released version 0.9 of the PCIe 5.0 specification to its members,<ref name="PCIe5r09" />
and on 17 January 2019, PCI SIG announced the version 0.9 had been ratified, with version 1.0 targeted for release in the first quarter of 2019.<ref name="ETVqe" />

On 29 May 2019, PCI-SIG officially announced the release of the final PCI Express 5.0 specification.<ref name="MW69U" />

On 20 November 2019, [[Jiangsu Huacun]] presented the first PCIe 5.0 Controller HC9001 in a 12&nbsp;nm manufacturing process<ref name="yk5Nd" /> and production started in 2020.

On 17 August 2020, IBM announced the [[Power10]] processor with PCIe 5.0 and up to 32 lanes per single-chip module (SCM) and up to 64 lanes per double-chip module (DCM).<ref>{{Cite web|url=https://hc32.hotchips.org/assets/program/conference/day1/HotChips2020_Server_Processors_IBM_Starke_POWER10_v33.pdf|title=IBM's POWER10 Processor, Hot Chips 32, August 16–18, 2020}}</ref>

On 9 September 2021, IBM announced the Power E1080 Enterprise server with planned availability date 17 September.<ref name="IBM-ENUSZG21-0059">[https://www.ibm.com/common/ssi/rep_ca/9/877/ENUSZG21-0059/index.html Power E1080 Enterprise server delivers a uniquely architected platform to help securely and efficiently scale core operational and AI applications in a hybrid cloud, IBM Europe Hardware Announcement ZG21-0059]</ref> It can have up to 16 Power10 SCMs with maximum of 32 slots per system which can act as PCIe 5.0 x8 or PCIe 4.0 x16.<ref name="IBM-REDP-5649-00">[http://www.redbooks.ibm.com/redpapers/pdfs/redp5649.pdf IBM Power E1080 Technical Overview and Introduction]</ref> Alternatively they can be used as PCIe 5.0 x16 slots for optional optical CXP converter adapters connecting to external PCIe expansion drawers.

On 27 October 2021, Intel announced the 12th Gen Intel Core CPU family, the world's first consumer x86-64 processors with PCIe 5.0 (up to 16 lanes) connectivity.<ref>{{cite web|url=https://www.intel.com/content/www/us/en/newsroom/news/12th-gen-core-processors.html |title=Intel Unveils 12th Gen Intel Core, Launches World's Best Gaming |date=31 December 2021 |publisher=Intel.com |accessdate=2022-02-16}}</ref>

On 22 March 2022, Nvidia announced Nvidia Hopper GH100 GPU, the world's first PCIe 5.0 GPU.<ref>{{cite web|url=https://nvidianews.nvidia.com/news/nvidia-announces-hopper-architecture-the-next-generation-of-accelerated-computing|title = NVIDIA Announces Hopper Architecture, the Next Generation of Accelerated Computing}}</ref>

On 23 May 2022, AMD announced its Zen 4 architecture with support for up to 24 lanes of PCIe 5.0 connectivity on consumer platforms and 128 lanes on server platforms.<ref>{{cite web|url=https://www.amd.com/en/press-releases/2022-05-23-amd-showcases-growth-gaming-commercial-and-mainstream-mobile-and-industry|title=AMD Showcases Industry-Leading Gaming, Commercial, and Mainstream PC Technologies at COMPUTEX 2022|publisher=AMD.com|accessdate=2022-05-23}}</ref><ref>{{cite web|url=
https://www.amd.com/en/campaigns/epyc-9004-architecture|title=4th Gen AMD EPYC™ Processor Architecture|publisher=AMD.com|accessdate=2022-11-12}}</ref>

=== PCI Express 6.0 <span class="anchor" id="6.0"></span> ===
On 18 June 2019, PCI-SIG announced the development of PCI Express 6.0 specification. Bandwidth is expected to increase to 64{{nbsp}}GT/s, yielding 128{{nbsp}}GB/s in each direction in a 16-lane configuration, with a target release date of 2021.<ref name="businesswire.com" /> The new standard uses 4-level [[pulse-amplitude modulation]] (PAM-4) with a low-latency [[forward error correction]] (FEC) in place of [[non-return-to-zero]] (NRZ) modulation.<ref name="O5gOe" /> Unlike previous PCI Express versions, forward error correction is used to increase data integrity and PAM-4 is used as line code so that two bits are transferred per transfer. With 64{{nbsp}}GT/s data transfer rate (raw bit rate), up to 121{{nbsp}}GB/s in each direction is possible in x16 configuration.<ref name="businesswire.com" />

On 24 February 2020, the PCI Express 6.0 revision 0.5 specification (a "first draft" with all architectural aspects and requirements defined) was released.<ref name="puGmx" />

On 5 November 2020, the PCI Express 6.0 revision 0.7 specification (a "complete draft" with electrical specifications validated via test chips) was released.<ref name="ltCSi" />

On 6 October 2021, the PCI Express 6.0 revision 0.9 specification (a "final draft") was released.<ref name="60r9">{{cite web |last=Yanes |first=Al |title=PCIe® 6.0 Specification, Version 0.9: One Step Closer to Final Release {{!}} PCI-SIG |url=https://pcisig.com/blog/pcie®-60-specification-version-09-one-step-closer-final-release |website=pcisig.com |access-date=6 October 2021}}</ref>

On 11 January 2022, PCI-SIG officially announced the release of the final PCI Express 6.0 specification.<ref>{{cite web|url=https://www.businesswire.com/news/home/20220111005011/en/PCI-SIG%C2%AE-Releases-PCIe%C2%AE-6.0-Specification-Delivering-Record-Performance-to-Power-Big-Data-Applications |title=PCI-SIG® Releases PCIe® 6.0 Specification Delivering Record Performance to Power Big Data Applications |publisher=Business Wire |date=2022-01-11 |accessdate=2022-02-16}}</ref>

[[PAM-4]] coding results in a vastly higher [[bit error rate]] (BER) of 10<sup>−6</sup> (vs. 10<sup>−12</sup> previously), so in place of 128b/130b encoding, a 3-way interlaced [[forward error correction]] (FEC) is used in addition to [[cyclic redundancy check]] (CRC). A fixed 256 byte [[Flit (computer networking)|Flow Control Unit]] (FLIT) block carries 242 bytes of data, which includes variable-sized transaction level packets (TLP) and data link layer payload (DLLP); remaining 14 bytes are reserved for 8-byte CRC and 6-byte FEC.<ref name=pcie6_evolution_blog>{{cite web|url=https://pcisig.com/blog/evolution-pci-express-specification-its-sixth-generation-third-decade-and-still-going-strong |title=The Evolution of the PCI Express Specification: On its Sixth Generation, Third Decade and Still Going Strong |publisher=Pci-Sig |date=2022-01-11 |accessdate=2022-02-16}}</ref><ref name="PCIe6_fut">{{cite web|url=https://www.youtube.com/watch?v=jhehXwnu0Ss | archive-url=https://ghostarchive.org/varchive/youtube/20211030/jhehXwnu0Ss| archive-date=2021-10-30|title=PCIe 6.0 Specification: The Interconnect for I/O Needs of the Future |page=8 |author=Debendra Das Sharma | date=8 June 2020|publisher=PCI-SIG}}{{cbignore}}</ref> 3-way [[Gray code]] is used in PAM-4/FLIT mode to reduce error rate; the interface does not switch to NRZ and 128/130b encoding even when retraining to lower data rates.<ref name=cadence_pice6>{{cite web|url=https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/ip/design-ip/pushing-the-envelope-with-pcie-6-wp.pdf |title=Pushing the Envelope with PCIe 6.0: Bringing PAM4 to PCIe |date= |accessdate=2022-02-16}}</ref><ref name=pcie6_webinar>{{cite web|url=https://pcisig.com/sites/default/files/files/PCIe%206.0%20Webinar_Final_.pdf |title=PowerPoint Presentation |date= |accessdate=2022-02-16}}</ref>

=== PCI Express 7.0 <span class="anchor" id="7.0"></span> ===
On 21 June 2022, PCI-SIG announced the development of PCI Express 7.0 specification.<ref>{{cite web|url=https://www.businesswire.com/news/home/20220621005137/en |title=PCI-SIG® Announces PCI Express® 7.0 Specification to Reach 128 GT/s |publisher=Business Wire |date=2022-06-21 |accessdate=2022-06-25}}</ref> It will deliver 128&nbsp;GT/s raw bit rate and up to 242&nbsp;GB/s per direction in x16 configuration, using the same [[Pulse-amplitude modulation|PAM4]] signaling as version 6.0. Doubling of the data rate will be achieved by fine-tuning channel parameters to decrease signal losses and improve power efficiency, but signal integrity is expected to be a challenge. The specification is expected to be finalized in 2025.

On 3 April 2024, the PCI Express 7.0 revision 0.5 specification (a "first draft") was released.<ref name="PCIe70v05"/>

On 17 January 2025, PCI-SIG announced the release of PCIe 7.0 specification version 0.7 (a "complete draft").<ref name="PCIe70v07"/>

On 19 March 2025, PCI-SIG announced the release of PCIe 7.0 specification version 0.9 (a "final draft"); planned final release is still in 2025.<ref name="PCIe70v09"/>

The following main points were formulated as objectives of the new standard:
* Delivering 128 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration
* Utilizing PAM4 (Pulse Amplitude Modulation with 4 levels) signaling
* Focusing on the channel parameters and reach
* Improving power efficiency
* Continuing to deliver the low-latency and high-reliability targets
* Maintaining backwards compatibility with all previous generations of PCIe technology