Editing Static random-access memory (section)

== Production challenges ==
Over 30 years (from 1987 to 2017), with a steadily decreasing [[Semiconductor device fabrication|transistor size]] (node size), the footprint-shrinking of the SRAM cell topology itself slowed down, making it harder to pack the cells more densely.<ref name=":0" /> One of the reasons is that scaling down transistor size leads to SRAM reliability issues. Careful cells designs are necessary to achieve SRAM cells that do not suffer from stability problems especially when they are being read.<ref>{{Cite journal |last1=Torrens |first1=Gabriel |last2=Alorda |first2=Bartomeu |last3=Carmona |first3=Cristian |last4=Malagon-Perianez |first4=Daniel |last5=Segura |first5=Jaume |last6=Bota |first6=Sebastia |date=2019 |title=A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors |url=https://ieeexplore.ieee.org/document/7981367 |journal=IEEE Transactions on Emerging Topics in Computing |volume=7 |issue=3 |pages=447–455 |arxiv=2411.18114 |doi=10.1109/TETC.2017.2721932 |issn=2168-6750}}</ref> With the introduction of the [[FinFET]] transistor implementation of SRAM cells, they started to suffer from increasing inefficiencies in cell sizes.

Besides issues with size a significant challenge of modern SRAM cells is a static current leakage. The current, that flows from positive supply (V<sub>dd</sub>), through the cell, and to the ground, increases exponentially when the cell's temperature rises. The cell power drain occurs in both active and idle states, thus wasting useful energy without any useful work done. Even though in the last 20 years the issue was partially addressed by the Data Retention Voltage technique (DRV) with reduction rates ranging from 5 to 10, the decrease in node size caused reduction rates to fall to about 2.<ref name=":0" />

With these two issues it became more challenging to develop energy-efficient and dense SRAM memories, prompting semiconductor industry to look for alternatives such as [[STT-MRAM]] and [[F-RAM]].<ref name=":0" /><ref>{{Cite web|last=Walker|first=Andrew|date=February 6, 2019|title=The Race is On|url=https://www.eetimes.com/the-race-is-on/|publisher=[[EE Times]]}}</ref>

=== Research ===
In 2019 a French institute reported on a research of an [[IoT]]-purposed [[Semiconductor device fabrication|28nm]] fabricated [[Integrated circuit|IC]].<ref name=":1">{{Cite web|last=Reda|first=Boumchedda|date=May 20, 2019|title=Ultra-low voltage and energy efficient SRAM design with new technologies for IoT applications|url=https://tel.archives-ouvertes.fr/tel-03359929/document|publisher=[[Grenoble Alpes University]]}}</ref> It was based on [[Silicon on insulator|fully depleted silicon on insulator]]-transistors (FD-SOI), had two-ported SRAM memory rail for synchronous/asynchronous accesses, and selective [[virtual ground]] (SVGND). The study claimed reaching an ultra-low SVGND current in a ''sleep'' and read modes by finely tuning its voltage.<ref name=":1" />