Editing Static random-access memory (section)

=== Research ===
In 2019 a French institute reported on a research of an [[IoT]]-purposed [[Semiconductor device fabrication|28nm]] fabricated [[Integrated circuit|IC]].<ref name=":1">{{Cite web|last=Reda|first=Boumchedda|date=May 20, 2019|title=Ultra-low voltage and energy efficient SRAM design with new technologies for IoT applications|url=https://tel.archives-ouvertes.fr/tel-03359929/document|publisher=[[Grenoble Alpes University]]}}</ref> It was based on [[Silicon on insulator|fully depleted silicon on insulator]]-transistors (FD-SOI), had two-ported SRAM memory rail for synchronous/asynchronous accesses, and selective [[virtual ground]] (SVGND). The study claimed reaching an ultra-low SVGND current in a ''sleep'' and read modes by finely tuning its voltage.<ref name=":1" />