Editing ARM architecture family (section)

====Pipelines and other implementation issues====
The ARM7 and earlier implementations have a three-stage [[instruction pipelining|pipeline]]; the stages being fetch, decode, and execute. Higher-performance designs, such as the ARM9, have deeper pipelines: Cortex-A8 has thirteen stages. Additional implementation changes for higher performance include a faster [[adder (electronics)|adder]] and more extensive [[branch prediction]] logic. The difference between the ARM7DI and ARM7DMI cores, for example, was an improved multiplier; hence the added "M".