Editing Consistency model (section)

=== Relaxed write to read ===

An approach to improving the performance at the hardware level is by relaxing the PO of a write followed by a read which effectively hides the latency of write operations. The optimisation this type of relaxation relies on is that it allows the subsequent reads to be in a relaxed order with respect to the previous writes from the processor. Because of this relaxation some programs like XXX may fail to give SC results because of this relaxation. Whereas, programs like YYY are still expected to give consistent results because of the enforcement of the remaining program order constraints.

Three models fall under this category. The IBM 370 model is the strictest model. A read can be complete before an earlier write to a different address, but it is prohibited from returning the value of the write unless all the processors have seen the write. The SPARC V8 total store ordering model (TSO) model partially relaxes the IBM 370 Model, it allows a read to return the value of its own processor's write with respect to other writes to the same location i.e. it returns the value of its own write before others see it. Similar to the previous model, this cannot return the value of write unless all the processors have seen the write. The processor consistency model (PC) is the most relaxed of the three models and relaxes both the constraints such that a read can complete before an earlier write even before it is made visible to other processors.

In Example A, the result is possible only in IBM 370 because read(A) is not issued until the write(A) in that processor is completed. On the other hand, this result is possible in TSO and PC because they allow the reads of the flags before the writes of the flags in a single processor.

In Example B the result is possible only with PC as it allows P2 to return the value of a write even before it is visible to P3. This won't be possible in the other two models.

To ensure sequential consistency in the above models, safety nets or fences are used to manually enforce the constraint. The IBM370 model has some specialised ''serialisation instructions'' which are manually placed between operations. These instructions can consist of memory instructions or non-memory instructions such as branches. On the other hand, the TSO and PC models do not provide safety nets, but the programmers can still use read-modify-write operations to make it appear like the program order is still maintained between a write and a following read. In case of TSO, PO appears to be maintained if the R or W which is already a part of a R-modify-W is replaced by a R-modify-W, this requires the W in the R-modify-W is a ‘dummy’ that returns the read value. Similarly for PC, PO seems to be maintained if the read is replaced by a write or is already a part of R-modify-W.

However, compiler optimisations cannot be done after exercising this relaxation alone. Compiler optimisations require the full flexibility of reordering any two operations in the PO, so the ability to reorder a write with respect to a read is not sufficiently helpful in this case.

{| class="wikitable"
|+ Example A
|-
! {{abbr|P|Processor}}1
! {{abbr|P|Processor}}2
|-
| colspan=2 style="text-align:center;" | A = flag1 = flag2 = 0
|-
| flag1 = 1    || flag2 = 1
|-
| A = 1        || A = 2
|-
| reg1 = A     || reg3 = A
|- 
| reg2 = flag2 || reg4 = flag1
|-
| colspan=2 style="text-align:center;" | reg1 = 1; reg3 = 2, reg2 = reg4 = 0
|}

{| class="wikitable"
|+ Example B
|-
! {{abbr|P|Processor}}1
! {{abbr|P|Processor}}2
! {{abbr|P|Processor}}3
|-
| colspan=3 style="text-align:center;" | A = B = 0
|-
| A = 1 ||             ||
|-
|       || if (A == 1) ||
|-
|       || B = 1       || if (B == 1)
|-
|       ||             || reg1 = A
|-
| colspan=3 style="text-align:center;" | B = 1, reg1 = 0
|}