Editing MOSFET (section)

== Scaling ==
{{Essay|section|date=September 2016}}
{{Further|Dennard scaling}}
[[file:Intel gate length trend.PNG|thumb|upright=1.2|Trend of Intel CPU transistor gate length]]
[[file:WIde-swing MOSFET mirror.PNG|thumb|upright=1.2|MOSFET version of gain-boosted [[current mirror]]; M<sub>1</sub> and M<sub>2</sub> are in active mode, while M<sub>3</sub> and M<sub>4</sub> are in Ohmic mode, and act like resistors. The operational amplifier provides feedback that maintains a high output resistance.]]

Over the past decades, the MOSFET (as used for digital logic) has continually been scaled down in size; typical MOSFET channel lengths were once several [[micrometre]]s, but modern integrated circuits are incorporating MOSFETs with channel lengths of tens of nanometers. [[Robert Dennard]]'s work on [[scaling law|scaling theory]] was pivotal in recognising that this ongoing reduction was possible. Intel began production of a process featuring a 32&nbsp;nm feature size (with the channel being even shorter) in late 2009. The semiconductor industry maintains a "roadmap", the [[International Technology Roadmap for Semiconductors|ITRS]],<ref>{{cite web |url=http://www.itrs.net |title=International Technology Roadmap for Semiconductors |url-status=dead |archive-url=https://web.archive.org/web/20151228041321/http://www.itrs.net/ |archive-date=2015-12-28 }}</ref> which sets the pace for MOSFET development. Historically, the difficulties with decreasing the size of the MOSFET have been associated with the semiconductor device fabrication process, the need to use very low voltages, and with poorer electrical performance necessitating circuit redesign and innovation (small MOSFETs exhibit higher leakage currents and lower output resistance).

Smaller MOSFETs are desirable for several reasons. The main reason to make transistors smaller is to pack more and more devices in a given chip area. This results in a chip with the same functionality in a smaller area, or chips with more functionality in the same area. Since fabrication costs for a [[semiconductor wafer]] are relatively fixed, the cost per integrated circuits is mainly related to the number of chips that can be produced per wafer. Hence, smaller ICs allow more chips per wafer, reducing the price per chip. In fact, over the past 30 years the number of transistors per chip has been doubled every 2–3 years once a new technology node is introduced. For example, the number of MOSFETs in a microprocessor fabricated in a [[45 nm]] technology can well be twice as many as in a [[65 nm]] chip. This doubling of transistor density was first observed by [[Gordon Moore]] in 1965 and is commonly referred to as [[Moore's law]].<ref>{{cite web | title = 1965&nbsp;– "Moore's Law" Predicts the Future of Integrated Circuits | work = Computer History Museum | url = http://www.computerhistory.org/semiconductor/timeline/1965-Moore.html}}</ref> It is also expected that smaller transistors switch faster. For example, one approach to size reduction is a scaling of the MOSFET that requires all device dimensions to reduce proportionally. The main device dimensions are the channel length, channel width, and oxide thickness. When they are scaled down by equal factors, the transistor channel resistance does not change, while gate capacitance is cut by that factor. Hence, the [[RC delay]] of the transistor scales with a similar factor. While this has been traditionally the case for the older technologies, for the state-of-the-art MOSFETs reduction of the transistor dimensions does not necessarily translate to higher chip speed because the delay due to interconnections is more significant.

Producing MOSFETs with channel lengths much smaller than a [[micrometre]] is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology. Though processes such as [[atomic layer deposition|ALD]] have improved fabrication for small components, the small size of the MOSFET (less than a few tens of nanometers) has created operational problems:

===Higher subthreshold conduction===
As MOSFET geometries shrink, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available; the circuit design is a compromise between strong current in the ''on'' case and low current in the ''off'' case, and the application determines whether to favor one over the other. Subthreshold leakage (including subthreshold conduction, gate-oxide leakage and reverse-biased junction leakage), which was ignored in the past, now can consume upwards of half of the total power consumption of modern high-performance VLSI chips.<ref name=Roy>{{ cite book | first1 =Kaushik|last1=Roy |first2=Kiat Seng|last2=Yeo | title=Low Voltage, Low Power VLSI Subsystems | year = 2004 | page = Fig. 2.1, p. 44, Fig. 1.1, p. 4 | publisher = McGraw-Hill Professional | isbn = 978-0-07-143786-8 | url = https://books.google.com/books?id=jXm4pNxCSCYC&pg=PA4 | no-pp = true }}</ref><ref name=Goodnick>{{ cite book | first1 =Dragica|last1=Vasileska |author1-link=Dragica Vasileska|first2=Stephen|last2=Goodnick | title=Computational Electronics | year = 2006 | page = 103 | publisher = Morgan & Claypool | isbn = 978-1-59829-056-1 | url = https://books.google.com/books?id=DBPnzqy5Fd8C&pg=PA103 }}</ref>

===Increased gate-oxide leakage===
The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. However, with current gate oxides with a thickness of around 1.2&nbsp;[[nanometer|nm]] (which in silicon is ~5&nbsp;[[atom]]s thick) the [[quantum mechanical]] phenomenon of [[electron tunneling]] occurs between the gate and channel, leading to increased power consumption. [[Silicon dioxide]] has traditionally been used as the gate insulator. Silicon dioxide however has a modest dielectric constant. Increasing the dielectric constant of the gate dielectric allows a thicker layer while maintaining a high capacitance (capacitance is proportional to dielectric constant and inversely proportional to dielectric thickness). All else equal, a higher dielectric thickness reduces the [[quantum tunneling]] current through the dielectric between the gate and the channel.

Insulators that have a larger [[dielectric constant]] than silicon dioxide (referred to as [[high-κ dielectric]]s), such as group IVb metal silicates e.g. [[hafnium]] and [[zirconium]] silicates and oxides are being used to reduce the gate leakage from the 45 nanometer technology node onwards. On the other hand, the barrier height of the new gate insulator is an important consideration; the difference in [[conduction band]] energy between the semiconductor and the dielectric (and the corresponding difference in [[valence band]] energy) also affects leakage current level. For the traditional gate oxide, silicon dioxide, the former barrier is approximately 8 [[Electronvolt|eV]]. For many alternative dielectrics the value is significantly lower, tending to increase the tunneling current, somewhat negating the advantage of higher dielectric constant. The maximum gate-source voltage is determined by the strength of the electric field able to be sustained by the gate dielectric before significant leakage occurs. As the insulating dielectric is made thinner, the electric field strength within it goes up for a fixed voltage. This necessitates using lower voltages with the thinner dielectric.

===Increased junction leakage===
To make devices smaller, junction design has become more complex, leading to higher [[Doping (semiconductors)|doping]] levels, shallower junctions, "halo" doping and so forth,<ref>{{cite web|url=http://frontiersemi.com/pdf/papers/RsLransist.pdf |title=Frontier Semiconductor Paper |accessdate=2012-06-02 |url-status=dead |archiveurl=https://web.archive.org/web/20120227064415/http://frontiersemi.com/pdf/papers/RsLransist.pdf |archivedate=February 27, 2012 }}</ref><ref name=Chen>{{ cite book | first = Wai-Kai|last=Chen | title = The VLSI Handbook | page = Fig. 2.28, p. 2–22 | year = 2006 | publisher = CRC Press | isbn = 978-0-8493-4199-1 | url = https://books.google.com/books?id=NDdsjtTLTd0C&pg=PT49 | no-pp = true}}</ref> all to decrease drain-induced barrier lowering (see the section on [[#Junction design|junction design]]). To keep these complex junctions in place, the annealing steps formerly used to remove damage and electrically active defects must be curtailed<ref>{{cite journal |doi=10.1557/PROC-765-D7.4 |first1=R. |last1=Lindsay |title=A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS |journal=MRS Proceedings |volume=765 |year=2011 |last2=Pawlak |last3=Kittl |last4=Henson |last5=Torregiani |last6=Giangrandi |last7=Surdeanu |last8=Vandervorst |last9=Mayur |last10=Ross |last11=McCoy |last12=Gelpey |last13=Elliott |last14=Pages |last15=Satta |last16=Lauwers |last17=Stolk |last18=Maex}}</ref> increasing junction leakage. Heavier doping is also associated with thinner depletion layers and more recombination centers that result in increased leakage current, even without lattice damage.

===Drain-induced barrier lowering and ''V''<sub>T</sub> roll off===
[[Drain-induced barrier lowering]] (DIBL) and ''V''<sub>T</sub> roll off: Because of the [[short-channel effect]], channel formation is not entirely done by the gate, but now the drain and source also affect the channel formation. As the channel length decreases, the depletion regions of the source and drain come closer together and make the threshold voltage (''V''<sub>T</sub>) a function of the length of the channel. This is called ''V''<sub>T</sub> roll-off. ''V''<sub>T</sub> also becomes function of drain to source voltage ''V''<sub>DS</sub>. As we increase the ''V''<sub>DS</sub>, the depletion regions increase in size, and a considerable amount of charge is depleted by the ''V''<sub>DS</sub>. The gate voltage required to form the channel is then lowered, and thus, the ''V''<sub>T</sub> decreases with an increase in ''V''<sub>DS</sub>. This effect is called drain induced barrier lowering (DIBL).

===Lower output resistance===
For analog operation, good gain requires a high MOSFET output impedance, which is to say, the MOSFET current should vary only slightly with the applied drain-to-source voltage. As devices are made smaller, the influence of the drain competes more successfully with that of the gate due to the growing proximity of these two electrodes, increasing the sensitivity of the MOSFET current to the drain voltage. To counteract the resulting decrease in output resistance, circuits are made more complex, either by requiring more devices, for example the [[cascode]] and [[cascade amplifier]]s, or by feedback circuitry using [[operational amplifiers]], for example a circuit like that in the adjacent figure.

===Lower transconductance===
The [[transconductance]] of the MOSFET decides its gain and is proportional to hole or [[electron mobility]] (depending on device type), at least for low drain voltages. As MOSFET size is reduced, the fields in the channel increase and the dopant impurity levels increase. Both changes reduce the carrier mobility, and hence the transconductance. As channel lengths are reduced without proportional reduction in drain voltage, raising the electric field in the channel, the result is velocity saturation of the carriers, limiting the current and the transconductance.

===Interconnect capacitance===
Traditionally, switching time was roughly proportional to the gate capacitance of gates. However, with transistors becoming smaller and more transistors being placed on the chip, [[capacitance|interconnect capacitance]] (the capacitance of the metal-layer connections between different parts of the chip) is becoming a large percentage of capacitance.<ref>{{cite web|url=http://www.research.ibm.com/journal/rd/293/ibmrd2903G.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.research.ibm.com/journal/rd/293/ibmrd2903G.pdf |archive-date=2022-10-09 |url-status=live|title=VLSI wiring capacitance|date=9 February 2021 |publisher=IBM Journal of Research and Development}}{{dead link|date=June 2015}}</ref><ref name=Soudris>{{ cite book | editor1-first = D.|editor1-last= Soudris|editor2-first=P.|editor2-last=Pirsch|editor3-first=E.|editor3-last=Barke | title = Integrated Circuit Design: Power and Timing Modeling, Optimization, and Simulation (10th Int. Workshop) | year = 2000 | page = 38 | publisher = Springer | isbn = 978-3-540-41068-3 | url = https://books.google.com/books?id=TGQxMLsGzVUC&pg=PA38}}</ref> Signals have to travel through the interconnect, which leads to increased delay and lower performance.

===Heat production===
The ever-increasing density of MOSFETs on an integrated circuit creates problems of substantial localized heat generation that can impair circuit operation. Circuits operate more slowly at high temperatures, and have reduced reliability and shorter lifetimes. Heat sinks and other cooling devices and methods are now required for many integrated circuits including microprocessors. [[Power MOSFET]]s are at risk of [[thermal runaway]]. As their on-state resistance rises with temperature, if the load is approximately a constant-current load then the power loss rises correspondingly, generating further heat. When the [[heatsink]] is not able to keep the temperature low enough, the junction temperature may rise quickly and uncontrollably, resulting in destruction of the device.

===Process variations===
With MOSFETs becoming smaller, the number of atoms in the silicon that produce many of the transistor's properties is becoming fewer, with the result that control of dopant numbers and placement is more erratic. During chip manufacturing, random process variations affect all transistor dimensions: length, width, junction depths, oxide thickness ''etc.'', and become a greater percentage of overall transistor size as the transistor shrinks. The transistor characteristics become less certain, more statistical. The random nature of manufacture means we do not know which particular example MOSFETs actually will end up in a particular instance of the circuit. This uncertainty forces a less optimal design because the design must work for a great variety of possible component MOSFETs. See [[Process variation (semiconductor)|process variation]], [[design for manufacturability]], [[reliability engineering]], and [[statistical process control]].<ref name=Boning>{{ cite book |first1=Michael|last1=Orshansky |first2=Sani |last2=Nassif |first3=Duane |last3=Boning |title=Design for Manufacturability And Statistical Design: A Constructive Approach |date=2007 | publisher=Springer |location=New York |url=https://www.amazon.com/gp/reader/0387309284/ref=sib_dp_pt/002-1766819-0058402#reader-link|isbn=9780387309286 }}</ref>

===Modeling challenges===
Modern ICs are computer-simulated with the goal of obtaining working circuits from the first manufactured lot. As devices are miniaturized, the complexity of the processing makes it difficult to predict exactly what the final devices look like, and modeling of physical processes becomes more challenging as well. In addition, microscopic variations in structure due simply to the probabilistic nature of atomic processes require statistical (not just deterministic) predictions. These factors combine to make adequate simulation and "right the first time" manufacture difficult.