Editing Parallel computing (section)

=====Application-specific integrated circuits=====
{{main|Application-specific integrated circuit}}
Several [[application-specific integrated circuit]] (ASIC) approaches have been devised for dealing with parallel applications.<ref>Maslennikov, Oleg (2002). [https://doi.org/10.1007%2F3-540-48086-2_30 "Systematic Generation of Executing Programs for Processor Elements in Parallel ASIC or FPGA-Based Systems and Their Transformation into VHDL-Descriptions of Processor Element Control Units".] ''Lecture Notes in Computer Science'', '''2328/2002:''' p.&nbsp;272.</ref><ref>{{cite book|last=Shimokawa|first=Y.|author2=Fuwa, Y. |author3=Aramaki, N. |title=&#91;Proceedings&#93; 1991 IEEE International Joint Conference on Neural Networks |chapter=A parallel ASIC VLSI neurocomputer for a large number of neurons and billion connections per second speed |date=18–21 November 1991|volume=3|pages=2162–2167|doi=10.1109/IJCNN.1991.170708|isbn=978-0-7803-0227-3|s2cid=61094111}}</ref><ref>{{cite journal|last=Acken|first=Kevin P.|author2=Irwin, Mary Jane |author3=Owens, Robert M.|title=A Parallel ASIC Architecture for Efficient Fractal Image Coding |journal=The Journal of VLSI Signal Processing|date=July 1998|volume=19|issue=2|pages=97–113|doi=10.1023/A:1008005616596|bibcode=1998JSPSy..19...97A |s2cid=2976028}}</ref>

Because an ASIC is (by definition) specific to a given application, it can be fully optimized for that application. As a result, for a given application, an ASIC tends to outperform a general-purpose computer. However, ASICs are created by [[photolithography|UV photolithography]]. This process requires a mask set, which can be extremely expensive. A mask set can cost over a million US dollars.<ref>Kahng, Andrew B. (June 21, 2004) "[http://www.future-fab.com/documents.asp?grID=353&d_ID=2596 Scoping the Problem of DFM in the Semiconductor Industry] {{webarchive|url=https://web.archive.org/web/20080131221732/http://www.future-fab.com/documents.asp?grID=353&d_ID=2596 |date=2008-01-31 }}." University of California, San Diego. "Future design for manufacturing (DFM) technology must reduce design [non-recoverable expenditure] cost and directly address manufacturing [non-recoverable expenditures]—the cost of a mask set and probe card—which is well over $1&nbsp;million at the 90&nbsp;nm technology node and creates a significant damper on semiconductor-based innovation."</ref> (The smaller the transistors required for the chip, the more expensive the mask will be.) Meanwhile, performance increases in general-purpose computing over time (as described by [[Moore's law]]) tend to wipe out these gains in only one or two chip generations.<ref name="DAmour"/> High initial cost, and the tendency to be overtaken by Moore's-law-driven general-purpose computing, has rendered ASICs unfeasible for most parallel computing applications. However, some have been built. One example is the PFLOPS [[RIKEN MDGRAPE-3]] machine which uses custom ASICs for [[molecular dynamics]] simulation.