Editing CPU cache (section)

====Victim cache====
{{Main article|Victim cache}}
A '''victim cache''' is a cache used to hold blocks evicted from a CPU cache upon replacement. The victim cache lies between the main cache and its refill path, and holds only those blocks of data that were evicted from the main cache. The victim cache is usually fully associative, and is intended to reduce the number of conflict misses. Many commonly used programs do not require an associative mapping for all the accesses. In fact, only a small fraction of the memory accesses of the program require high associativity. The victim cache exploits this property by providing high associativity to only these accesses. It was introduced by [[Norman Jouppi]] from DEC in 1990.<ref name=Jouppi1990>{{cite conference 
 |last=Jouppi |first=Norman P.
 |date=May 1990
 |title=Improving direct-mapped cache performance by the addition of a small {{Sic|hide=y|fully|-}}associative cache and prefetch buffers
 |pages=364–373
 |book-title=Conference Proceedings of the 17th Annual International Symposium on Computer Architecture
 |conference=17th Annual International Symposium on Computer Architecture, May 28-31, 1990
 |location=Seattle, WA, USA
 |doi=10.1109/ISCA.1990.134547
}}</ref>

Intel's ''[[Crystalwell]]''<ref name="intel-ark-crystal-well">{{cite web
 | url = http://ark.intel.com/products/codename/51802/Crystal-Well
 | title = Products (Formerly Crystal Well)
 | publisher = [[Intel]]
 | access-date = 2013-09-15
}}</ref> variant of its [[Haswell (microarchitecture)|Haswell]] processors introduced an on-package 128&nbsp;MiB [[eDRAM]] Level 4 cache which serves as a victim cache to the processors' Level 3 cache.<ref name="anandtech-i74950hq">{{cite web
 | url = http://www.anandtech.com/show/6993/intel-iris-pro-5200-graphics-review-core-i74950hq-tested/3
 | title =  Intel Iris Pro 5200 Graphics Review: Core i7-4950HQ Tested
 | publisher = [[AnandTech]]
 | access-date = 2013-09-16
}}</ref> In the [[Skylake (microarchitecture)|Skylake]] microarchitecture the Level 4 cache no longer works as a victim cache.<ref>{{cite web |author=Cutress |first=Ian |date=September 2, 2015 |title=The Intel Skylake Mobile and Desktop Launch, with Architecture Analysis |url=http://www.anandtech.com/show/9582/intel-skylake-mobile-desktop-launch-architecture-analysis/5 |publisher=AnandTech}}</ref>