Editing Dynamic random-access memory (section)

===Asynchronous DRAM===
The original DRAM, now known by the [[retronym]] ''asynchronous DRAM'' was the first type of DRAM in use. From its origins in the late 1960s, it was commonplace in computing up until around 1997, when it was mostly replaced by ''synchronous DRAM''. In the present day, manufacture of asynchronous RAM is relatively rare.<ref>{{cite web|url=http://www.radio-electronics.com/info/data/semicond/memory/sdram-memory-basics-tutorial.php|title=SDRAM Memory Basics & Tutorial|author=Ian Poole|access-date=26 Feb 2018|url-status=live|archive-url=https://web.archive.org/web/20180227153519/http://www.radio-electronics.com/info/data/semicond/memory/sdram-memory-basics-tutorial.php|archive-date=2018-02-27}}</ref>

====Principles of operation====
An asynchronous DRAM chip has power connections, some number of address inputs (typically 12), and a few (typically one or four) bidirectional data lines. There are three main [[active-low]] control signals:
* {{overline|RAS}}, the Row Address Strobe. The address inputs are captured on the falling edge of {{overline|RAS}}, and select a row to open. The row is held open as long as {{overline|RAS}} is low.
* {{overline|CAS}}, the Column Address Strobe. The address inputs are captured on the falling edge of {{overline|CAS}}, and select a column from the currently open row to read or write.
* {{overline|WE}}, Write Enable. This signal determines whether a given falling edge of {{overline|CAS}} is a read (if high) or write (if low). If low, the data inputs are also captured on the falling edge of {{overline|CAS}}.  If high, the data outputs are enabled by the falling edge of {{overline|CAS}} and produce valid output after the internal access time.

This interface provides direct control of internal timing: when {{overline|RAS}} is driven low, a {{overline|CAS}} cycle must not be attempted until the sense amplifiers have sensed the memory state, and {{overline|RAS}} must not be returned high until the storage cells have been refreshed. When {{overline|RAS}} is driven high, it must be held high long enough for precharging to complete.

Although the DRAM is asynchronous, the signals are typically generated by a clocked memory controller, which limits their timing to multiples of the controller's clock cycle.

For completeness, we mention two other control signals which are not essential to DRAM operation, but are provided for the convenience of systems using DRAM:
* {{overline|CS}}, Chip Select. When this is high, all other inputs are ignored.  This makes it easy to build an array of DRAM chips which share the same control signals.  Just as DRAM internally uses the word lines to select one row of storage cells connect to the shared bit lines and sense amplifiers, {{overline|CS}} is used to select one row of DRAM chips to connect to the shared control, address, and data lines.
* {{overline|OE}}, Output Enable. This is an additional signal that (if high) inhibits output on the data I/&zwj;O pins, while allowing all other operations to proceed normally.  In many applications, {{overline|OE}} can be permanently connected low (output enabled whenever {{overline|CS}}, {{overline|RAS}} and {{overline|CAS}} are low and {{overline|WE}} is high), but in high-speed applications, judicious use of {{overline|OE}} can prevent [[bus contention]] between two DRAM chips connected to the same data lines.  For example, it is possible to have two [[interleaved memory]] banks sharing the address and data lines, but each having their own {{overline|RAS}}, {{overline|CAS}}, {{overline|WE}} and {{overline|OE}} connections.  The memory controller can begin a read from the second bank while a read from the first bank is in progress, using the two {{overline|OE}} signals to only permit one result to appear on the data bus at a time.<!--There's also the Late Write or [[read–modify–write]] cycle where a read is changed to a write by a falling edge on /WE while /CAS remains low, which requires using /OE to drive the write data on the bus before the falling edge of /WE,<ref name=IBM96/>[https://classes.engineering.wustl.edu/cse260m/images/9/9e/MT4LC4M16R6.pdf] but that's rarely used in the real world.-->

=====RAS-only refresh=====
Classic asynchronous DRAM is refreshed by opening each row in turn.

The refresh cycles are distributed across the entire refresh interval in such a way that all rows are refreshed within the required interval. To refresh one row of the memory array using {{overline|RAS}} only refresh (ROR), the following steps must occur:
# The row address of the row to be refreshed must be applied at the address input pins.
# {{overline|RAS}} must switch from high to low. {{overline|CAS}} must remain high.<!--Refresh still works if there are /CAS accesses, it's just not "row-only" any more.-->
# At the end of the required amount of time, {{overline|RAS}} must return high.

This can be done by supplying a row address and pulsing {{overline|RAS}} low; it is not necessary to perform any {{overline|CAS}} cycles. An external counter is needed to iterate over the row addresses in turn.<ref name=IBM96>{{cite tech report |type=Application Note |title=Understanding DRAM Operation |url=http://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf|publisher=[[IBM]]|archive-url=https://web.archive.org/web/20170829153054/http://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf|archive-date=29 August 2017|date=December 1996}}</ref> In some designs, the CPU handled RAM refresh. The [[Zilog Z80]] is perhaps the best known example, as it has an internal row counter R which supplies the address for a special refresh cycle generated after each instruction fetch.<!--And data transfer in string instructions, and during HALT, but that's more detail than we need here.--><ref>{{cite tech report |title=Z80 CPU |type=User Manual |url=http://www.zilog.com/docs/z80/um0080.pdf#page=17 |page=3 |id=UM008011-0816 |year=2016}}</ref> In other systems, especially [[home computer]]s, refresh was handled by the video circuitry as a side effect of its periodic scan of the [[frame buffer]].<ref>{{cite web |url=https://retrocomputing.stackexchange.com/questions/14012/what-is-dram-refresh-and-why-is-the-weird-apple-ii-video-memory-layout-affected |title=What is DRAM refresh and why is the weird Apple II video memory layout affected by it? |date=3 March 2020}}</ref>

=====CAS before RAS refresh=====
For convenience, the counter was quickly incorporated into the DRAM chips themselves. If the {{overline|CAS}} line is driven low before {{overline|RAS}} (normally an illegal operation), then the DRAM ignores the address inputs and uses an internal counter to select the row to open.{{r|IBM96|TN-04-30}}  This is known as {{overline|CAS}}-before-{{overline|RAS}} (CBR) refresh. This became the standard form of refresh for asynchronous DRAM, and is the only form generally used with SDRAM.

=====Hidden refresh=====
Given support of {{overline|CAS}}-before-{{overline|RAS}} refresh, it is possible to deassert {{overline|RAS}} while holding {{overline|CAS}} low to maintain data output. If {{overline|RAS}} is then asserted again, this performs a CBR refresh cycle while the DRAM outputs remain valid. Because data output is not interrupted, this is known as ''hidden refresh''.<ref name=TN-04-30>{{cite tech report |type=Technical Note |title=Various Methods of DRAM Refresh |year=1994 |id=TN-04-30 |publisher=[[Micron Technology]] |url=http://www.downloads.reactivemicro.com/Public/Electronics/DRAM/DRAM%20Refresh.pdf |archive-url=https://web.archive.org/web/20111003001843/http://www.downloads.reactivemicro.com/Public/Electronics/DRAM/DRAM%20Refresh.pdf |archive-date=2011-10-03 |url-status=dead}}</ref>  Hidden refresh is no faster than a normal read followed by a normal refresh, but does maintain the data output valid during the refresh cycle.

====Page mode DRAM====
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'''Page mode DRAM''' is a minor modification to the first-generation DRAM IC interface which improves the performance of reads and writes to a row by avoiding the inefficiency of precharging and opening the same row repeatedly to access a different column. In page mode DRAM, after a row is opened by holding {{overline|RAS}} low, the row can be kept open, and multiple reads or writes can be performed to any of the columns in the row. Each column access is initiated by presenting a column address and asserting {{overline|CAS}}. For reads, after a delay (''t''<sub>CAC</sub>), valid data appears on the data out pins, which are held at high-Z before the appearance of valid data. For writes, the write enable signal and write data is presented along with the column address.<ref name="Kenner 13">{{harvnb|Keeth|Baker|Johnson|Lin|2007|p=13}}</ref>

Page mode DRAM was in turn later improved with a small modification which further reduced latency. DRAMs with this improvement are called '''fast page mode DRAMs''' ('''FPM DRAMs'''). In page mode DRAM, the chip does not capture the column address until {{overline|CAS}} is asserted, so column access time (until data out was valid) begins when {{overline|CAS}} is asserted.  In FPM DRAM, the column address can be supplied while {{overline|CAS}} is still deasserted, and the main column access time (''t''<sub>AA</sub>) begins as soon as the address is stable.  The {{overline|CAS}} signal is only needed to enable the output (the data out pins were held at high-Z while {{overline|CAS}} was deasserted), so time from {{overline|CAS}} assertion to data valid (''t''<sub>CAC</sub>) is greatly reduced.<ref name="Kenner 14">{{harvnb|Keeth|Baker|Johnson|Lin|2007|p=14}}</ref> Fast page mode DRAM was introduced in 1986 and was used with the [[Intel 80486]].

''Static column'' is a variant of fast page mode in which the column address does not need to be latched, but rather the address inputs may be changed with {{overline|CAS}} held low, and the data output will be updated accordingly a few nanoseconds later.<ref name="Kenner 14" />

''Nibble mode'' is another variant in which four sequential locations within the row can be accessed with four consecutive pulses of {{overline|CAS}}. The difference from normal page mode is that the address inputs are not used for the second through fourth {{overline|CAS}} edges but are generated internally starting with the address supplied for the first {{overline|CAS}} edge.<ref name="Kenner 14" />  The predictable addresses let the chip prepare the data internally and respond very quickly to the subsequent {{overline|CAS}} pulses.

====Extended data out DRAM====
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[[Image:Pair32mbEDO-DRAMdimms.jpg|thumb|A pair of 32&nbsp;[[Megabyte|MB]] EDO DRAM modules]]

Extended data out DRAM (EDO DRAM) was invented and patented in the 1990s by [[Micron Technology]] who then licensed technology to many other memory manufacturers.<ref>{{cite book | author=S. Mueller | title=Upgrading and Repairing Laptops | year=2004 | publisher=Que; Har/Cdr Edition | page=221 | isbn=9780789728005 |url=https://books.google.com/books?id=xCXVGneKwScC}}</ref> EDO RAM, sometimes referred to as ''hyper page mode'' enabled DRAM, is similar to fast page mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (pipelining), allowing somewhat improved performance.<ref name=IBM96b>{{cite tech report |type=Applications Note |title=EDO (Hyper Page Mode)|url=https://www.ardent-tool.com/memory/pdf/edo.pdf |publisher=[[IBM]]|date=6 June 1996|archive-url=https://web.archive.org/web/20211202232211/https://ardent-tool.com/memory/pdf/edo.pdf|archive-date=2021-12-02|quote=a new address can be provided for the next access cycle before completing the current cycle allowing a shorter {{overline|CAS}} pulse width, dramatically decreasing cycle times.}}</ref> It is up to 30% faster than FPM DRAM,<ref>{{cite web|last1=Lin|first1=Albert|title=Memory Grades, the Most Confusing Subject|url=https://simmtester.com/News/PublicationArticle/11|website=Simmtester.com|publisher=CST, Inc.|access-date=1 November 2017|date=20 December 1999|url-status=live|archive-url=https://web.archive.org/web/20200812212321/https://simmtester.com/News/PublicationArticle/11|archive-date=2020-08-12|quote=So for the same –60 part, EDO DRAM is about 30% faster than FPM DRAM in peak data rate.}}</ref> which it began to replace in 1995 when [[Intel]] introduced the [[Mercury chipset|430FX chipset]] with EDO DRAM support. Irrespective of the performance gains, FPM and EDO SIMMs can be used interchangeably in many (but not all) applications.<ref>{{cite web|last1=Huang|first1=Andrew|title=Bunnie's RAM FAQ|url=http://www.bunniestudios.com/bunnie/dramfaq/DRAMFAQ.html|date=14 September 1996|url-status=live|archive-url=https://web.archive.org/web/20170612210850/http://www.bunniestudios.com/bunnie/dramfaq/DRAMFAQ.html|archive-date=12 June 2017}}</ref><ref>{{cite journal|author1=Cuppu, Vinodh|author2=Jacob, Bruce|author3=Davis, Brian|author4=Mudge, Trevor|title=High-Performance DRAMs in Workstation Environments|journal=IEEE Transactions on Computers|date=November 2001|volume=50|issue=11|pages=1133–1153|url=http://www.bunniestudios.com/bunnie/dramfaq/dram-workstation.pdf|access-date=2 November 2017|doi=10.1109/12.966491|hdl=1903/7456|url-status=live|archive-url=https://web.archive.org/web/20170808082644/http://www.bunniestudios.com/bunnie/dramfaq/dram-workstation.pdf|archive-date=8 August 2017|hdl-access=free}}</ref>

To be precise, EDO DRAM begins data output on the falling edge of {{overline|CAS}} but does not disable the output when {{overline|CAS}} rises again. Instead, it holds the current output valid (thus extending the data output time) even as the DRAM begins decoding a new column address, until either a new column's data is selected by another {{overline|CAS}} falling edge, or the output is switched off by the rising edge of {{overline|RAS}}.  (Or, less commonly, a change in {{overline|CS}}, {{overline|OE}}, or {{overline|WE}}.)

This ability to start a new access even before the system has received the preceding column's data made it possible to design memory controllers which could carry out a {{overline|CAS}} access (in the currently open row) in one clock cycle, or at least within two clock cycles instead of the previously required three. EDO's capabilities were able to partially compensate for the performance lost due to the lack of an L2 cache in low-cost, commodity PCs. More expensive notebooks also often lacked an L2 cache die to size and power limitations, and benefitted similarly. Even for systems ''with'' an L2 cache, the availability of EDO memory improved the average memory latency seen by applications over earlier FPM implementations.

Single-cycle EDO DRAM became very popular on video cards toward the end of the 1990s. It was very low cost, yet nearly as efficient for performance as the far more costly VRAM.

====Burst EDO DRAM====
An evolution of EDO DRAM, burst EDO DRAM (BEDO DRAM), could process four memory addresses in one burst, for a maximum of {{nowrap|5-1-1-1}}, saving an additional three clocks over optimally designed EDO memory. It was done by adding an address counter on the chip to keep track of the next address. BEDO also added a pipeline stage allowing page-access cycle to be divided into two parts. During a memory-read operation, the first part accessed the data from the memory array to the output stage (second latch). The second part drove the data bus from this latch at the appropriate logic level. Since the data is already in the output buffer, quicker access time is achieved (up to 50% for large blocks of data) than with traditional EDO.

Although BEDO DRAM showed additional optimization over EDO, by the time it was available the market had made a significant investment towards synchronous DRAM, or SDRAM.<ref>{{cite web|last=Kent |first=Dean |url=https://www.tomshardware.com/reviews/ram-guide,89-7.html |title=Burst EDO (BEDO) - Ram Guide {{pipe}} Tom's Hardware |publisher=Tomshardware.com |date= 24 October 1998|access-date=2022-03-09}}</ref>  Even though BEDO RAM was superior to SDRAM in some ways, the latter technology quickly displaced BEDO.