Editing PCI Express (section)

=== PCI Express 3.0 <span class="anchor" id="3.0"></span> ===
PCI Express 3.0 Base specification revision 3.0 was made available in November 2010, after multiple delays. In August 2007, PCI-SIG announced that PCI Express 3.0 would carry a bit rate of 8 [[gigatransfer]]s per second (GT/s), and that it would be backward compatible with existing PCI Express implementations. At that time, it was also announced that the final specification for PCI Express 3.0 would be delayed until Q2 2010.<ref name="cVjNG" /> New features for the PCI Express 3.0 specification included a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, [[phase-locked loop|PLL]] improvements, clock data recovery, and channel enhancements of currently supported topologies.<ref name="extrmetech" />

Following a six-month technical analysis of the feasibility of scaling the PCI Express interconnect bandwidth, PCI-SIG's analysis found that 8 gigatransfers per second could be manufactured in mainstream silicon process technology, and deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) with the PCI Express protocol stack.

PCI Express&nbsp;3.0 upgraded the [[encoding scheme]] to 128b/130b from the previous [[8b/10b encoding]], reducing the bandwidth overhead from 20% of  PCI Express&nbsp;2.0 to approximately 1.54% (=&nbsp;2/130). PCI Express 3.0's 8&nbsp;GT/s bit rate effectively delivers 985&nbsp;MB/s per lane, nearly doubling the lane bandwidth relative to PCI Express 2.0.<ref name="faq3" />

On 18 November 2010, the PCI Special Interest Group officially published the finalized PCI Express 3.0 specification to its members to build devices based on this new version of PCI Express.<ref name="ajVA3" />

==== PCI Express 3.1 <span class="anchor" id="3.1"></span> ====
In September 2013, PCI Express&nbsp;3.1 specification was announced for release in late 2013 or early 2014, consolidating various improvements to the published PCI Express&nbsp;3.0 specification in three areas: power management, performance and functionality.<ref name="PoRghEr" /><ref name="5lvIH" /> It was released in November 2014.<ref name="9EIkz" />