Editing Synchronous dynamic random-access memory (section)

=== Synchronous-link DRAM (SLDRAM) ===
SLDRAM boasted higher performance and competed against RDRAM. It was developed during the late 1990s by the SLDRAM Consortium. The SLDRAM Consortium consisted of about 20 major DRAM and computer industry manufacturers. (The SLDRAM Consortium became incorporated as SLDRAM Inc. and then changed its name to Advanced Memory International, Inc.) SLDRAM was an [[open standard]] and did not require licensing fees. The specifications called for a 64-bit bus running at a 200, 300 or 400&nbsp;MHz clock frequency. This is achieved by all signals being on the same line and thereby avoiding the synchronization time of multiple lines. Like [[DDR SDRAM]], SLDRAM uses a double-pumped bus, giving it an effective speed of 400,<ref>{{Citation |url=http://www.tomshardware.com/reviews/ram-guide,89-15.html |title=RAM Guide: SLDRAM |author=Dean Kent |publisher=Tom's Hardware |date=1998-10-24 |access-date=2011-01-01}}</ref> 600,<ref>{{Citation |url=http://icwic.cn/icwic/data/pdf/cd/cd011/12452.pdf |title=HYSL8M18D600A 600 Mb/s/pin 8M x 18 SLDRAM |type=data sheet |author=Hyundai Electronics |date=1997-12-20 |access-date=2011-12-27 |archive-url=https://web.archive.org/web/20120426081302/http://icwic.cn/icwic/data/pdf/cd/cd011/12452.pdf |archive-date=2012-04-26 |url-status=dead }}</ref> or 800&nbsp;[[MT/s]]. (1&nbsp;MT/s&nbsp;=&nbsp;1000<sup>2</sup> transfers per second)

SLDRAM used an 11-bit command bus (10 command bits CA9:0 plus one start-of-command FLAG line) to transmit 40-bit command packets on 4 consecutive edges of a differential command clock (CCLK/CCLK#). Unlike SDRAM, there were no per-chip select signals; each chip was assigned an ID when reset, and the command contained the ID of the chip that should process it. Data was transferred in 4- or 8-word bursts across an 18-bit (per chip) data bus, using one of two differential data clocks (DCLK0/DCLK0# and DCLK1/DCLK1#). Unlike standard SDRAM, the clock was generated by the data source (the SLDRAM chip in the case of a read operation) and transmitted in the same direction as the data, greatly reducing data skew. To avoid the need for a pause when the source of the DCLK changes, each command specified which DCLK pair it would use.<ref>{{Citation |url=http://icwic.cn/icwic/data/pdf/cd/cd011/12407.pdf |pages=32–33 |title=SLD4M18DR400 400 Mb/s/pin 4M x 18 SLDRAM |type=data sheet |author=SLDRAM Inc. |date=1998-07-09 |access-date=2011-12-27 |archive-url=https://web.archive.org/web/20120426081159/http://icwic.cn/icwic/data/pdf/cd/cd011/12407.pdf |archive-date=2012-04-26 |url-status=dead }}</ref>

The basic read/write command consisted of (beginning with CA9 of the first word):
{|class="wikitable" style="text-align:center"
|+ SLDRAM Read, write or row op request packet
! FLAG || CA9 || CA8 || CA7 || CA6 || CA5 || CA4 || CA3 || CA2 || CA1 || CA0
|-
! 1 
|colspan="9" bgcolor="#FFCCCC"| Device ID 8:0 ||bgcolor="#CCFFCC"| Co...
|-
! 0 
|colspan="5" bgcolor="#ccffcc"| ...mmand Code 5:0 ||colspan="3" bgcolor="#eeAAff"| Bank Addr. 2:0 ||colspan="2" bgcolor="#ffffcc"| Ro...
|-
! 0 
|colspan=9 bgcolor=#ffffcc| ...w Address 11:0 ||bgcolor=white| 0
|-
! 0 
|colspan="3" bgcolor="white"| 0 0 0 ||colspan="7" bgcolor="#ccffff"| Column address 6:0
|}

* 9 bits of Device ID
* 6 bits of Command Code
* 3 bits of Bank address
* 10 or 11 bits of row address
* 5 or 4 bits spare for row or column expansion
* 7 bits of column address

Individual devices had 8-bit IDs. The 9th bit of the ID sent in commands was used to address multiple devices. Any aligned power-of-2 sized group could be addressed. If the transmitted msbit was set, all least-significant bits up to and including the least-significant 0 bit of the transmitted address were ignored for "is this addressed to me?" purposes. (If the ID8 bit is actually considered less significant than ID0, the unicast address matching becomes a special case of this pattern.)

A read/write command had the msbit clear:
* CMD5=0
* CMD4=1 to open (activate) the specified row; CMD4=0 to use the currently open row
* CMD3=1 to transfer an 8-word burst; CMD3=0 for a 4-word burst
* CMD2=1 for a write, CMD2=0 for a read
* CMD1=1 to close the row after this access; CMD1=0 to leave it open
* CMD0 selects the DCLK pair to use (DCLK1 or DCLK0)

A notable omission from the specification was per-byte write enables; it was designed for systems with [[CPU cache|cache]]s and [[ECC memory]], which always write in multiples of a cache line.

Additional commands (with CMD5 set) opened and closed rows without a data transfer, performed refresh operations, read or wrote configuration registers, and performed other maintenance operations. Most of these commands supported an additional 4-bit sub-ID (sent as 5 bits, using the same multiple-destination encoding as the primary ID) which could be used to distinguish devices that were assigned the same primary ID because they were connected in parallel and always read/written at the same time.

There were a number of 8-bit control registers and 32-bit status registers to control various device timing parameters.