Editing Addressing mode (section)

==Obsolete addressing modes==
The addressing modes listed here were used in the 1950–1980 period, but are no longer available on most current computers.
This list is by no means complete; there have been many other interesting and peculiar addressing modes used from time to time, e.g.  absolute-minus-logical-OR of two or three index registers.<ref>{{cite book|url=http://bitsavers.org/pdf/ibm/704/24-6661-2_704_Manual_1955.pdf|title=704 Electronic Data-Processing Machine Manual of Operation|pages=10–11|publisher=[[IBM]]|year=1955}}</ref><ref>{{cite book|url=http://bitsavers.org/pdf/ibm/7090/22-6528-4_7090Manual.pdf|title=Reference Manual IBM 7090 Data Processing System|pages=9–10|publisher=IBM|year=1962}}</ref>

==={{anchor|multilevel memory indirect}}Multi-level memory indirect===
If the word size is larger than the address, then the word referenced for memory-indirect addressing could itself have an indirect flag set to indicate another memory indirect cycle. This flag is referred to as an '''indirection bit''', and the resulting pointer is a [[tagged pointer]], the indirection bit tagging whether it is a direct pointer or an indirect pointer. Care is needed to ensure that a chain of indirect addresses does not refer to itself; if it does, one can get an [[infinite loop]] while trying to resolve an address.

The [[IBM 1620]], the [[Data General Nova]], and the [[HP 2100]] series each have such a multi-level memory indirect, and could enter such an infinite address calculation loop. The memory indirect addressing mode on the Nova influenced the invention of [[threaded code#Development|indirect threaded code]].

The DEC [[PDP-10]] computer with [[18-bit computing|18-bit]] addresses and [[36-bit computing|36-bit]] words allowed multi-level indirect addressing with the possibility of using an index register at each stage as well.  The priority interrupt system was queried before decoding of every address word.<ref>{{cite book |title=DEC-10-HMAA-D: PDP-10 KA10 Central Processor Maintenance Manual |date=December 1968 |publisher=[[Digital Equipment Corporation]] |location=[[Maynard, Massachusetts]] |pages=2–11 |edition=1st Printing |url=http://bitsavers.org/pdf/dec/pdp10/KA10/DEC-10-HMAA_D_KA10_Maint_Dec68.pdf#page=23 |access-date=15 May 2021 |format=PDF |quote=Figure 2-9: Effective Address Calculation: test "PI RQ ?"}}</ref>  So, an indirect address loop would not prevent execution of device service routines, including any [[Preemption (computing)#Preemptive multitasking|preemptive multitasking]] scheduler's time-slice expiration handler.  A looping instruction would be treated like any other compute-bound job.

===Memory-mapped registers===
On some computers, there were addresses that referred to registers rather than to primary storage, or to primary memory used to implement those registers. Although on some early computers there were register addresses at the high end of the address range, e.g., [[IBM 650]],<ref>{{cite manual
 | title       = 650 magnetic drum data-processing machine - manual of operation
 | id          = 22-6060-2
 | date        = June 1955
 | page        = [http://www.bitsavers.org/pdf/ibm/650/22-6060-2_650_OperMan.pdf#page=8 9] 
 | section     = Storage
 | section-url = http://www.bitsavers.org/pdf/ibm/650/22-6060-2_650_OperMan.pdf#page=7
 | url         = http://www.bitsavers.org/pdf/ibm/650/22-6060-2_650_OperMan.pdf
 | accessdate  = March 14, 2022
 }}
</ref>{{efn|Condensor storage units for 650:
:8000 Console switches
:8001 Distributor
:8002 Lower accumulator
:8003 Upper accumulator
 }} [[IBM 7070]],<ref>{{cite manual
 | title       = Reference Manual - IBM 7070 Data Processing System
 | id          = A22-7003-0
 | date        = January 1960
 | page        = 252
 | section     = Core Storage and Register Addresses
 | section-url = http://www.bitsavers.org/pdf/ibm/7070/A22-7003-01_7070_Reference_Jan60.pdf#page=253
 | url         = http://www.bitsavers.org/pdf/ibm/7070/A22-7003-01_7070_Reference_Jan60.pdf
 | accessdate  = March 14, 2022
 }}
</ref>{{efn|For 5K or 10K 7070
:00xx Index register xx
:9991 Accumulator 1
:9992 Accumulator 2
:9993 Accumulator 3
:9995 Program register{{efn|Only valid from console|name=console}}
:9999 Instruction counter{{efn|name=console}}
 }} the trend has been to use only register address at the low end and to use only the first 8 or 16 words of memory (e.g. [[ICT 1900 series|ICL 1900]], DEC PDP-6/PDP-10). This meant that there was no need for a separate "add register to register" instruction – one could just use the "add memory to register" instruction.

In the case of early models of the PDP-10, which did not have any cache memory, if the "fast registers" option, which provided faster circuits to store the registers but still allowed them to be addressed as if they were in memory, was installed, a tight inner loop loaded into the first few words of memory ran much faster than it would have in magnetic core memory.

Later models of the DEC [[PDP-11]] series mapped the registers onto addresses in the input/output area, but this was primarily intended to allow remote diagnostics. Confusingly, the 16-bit registers were mapped onto consecutive 8-bit byte addresses.

===Memory indirect and autoincrement===
The DEC [[PDP-8]] minicomputer had eight special locations (at addresses 8 through 15). When accessed via memory indirect addressing, these locations would automatically increment prior to use.<ref>{{
Citation
 | last1 = Jones | first1 = Douglas
 | title = Reference Instructions on the PDP-8
 | url  = http://homepage.cs.uiowa.edu/~jones/pdp8/man/mri.html#autoindex
 | access-date = 1 July 2013
}}</ref> This made it easy to step through memory in a loop without needing to use the accumulator to increment the address.

The [[Data General Nova]] minicomputer had 16 special memory locations at addresses 16 through 31.<ref>{{
Citation
 | last1 = Friend | first1 = Carl
 | title = Data General NOVA Instruction Set Summary
 | url  = http://users.rcn.com/crfriend/museum/doco/DG/Nova/
 | access-date = 1 July 2013
}}</ref> When accessed via memory indirect addressing, 16 through 23 would automatically increment before use, and 24 through 31 would automatically decrement before use.

===Zero page===
The [[Data General Nova]], [[Motorola 6800]] family, and [[MOS Technology 6502]] family of processors had very few internal registers. Arithmetic and logical instructions were mostly performed against values in memory as opposed to internal registers. As a result, many instructions required a two-byte (16-bit) location to memory. Given that opcodes on these processors were only one byte (8 bits) in length, memory addresses could make up a significant part of code size.

Designers of these processors included a partial remedy known as "zero page" addressing. The initial 256 bytes of memory ($0000 – $00FF; a.k.a., page "0") could be accessed using a one-byte absolute or indexed memory address. This reduced instruction execution time by one clock cycle and instruction length by one byte. By storing often-used data in this region, programs could be made smaller and faster.

As a result, the zero page was used similarly to a register file. On many systems, however, this resulted in high utilization of the zero page memory area by the operating system and user programs, which limited its use since free space was limited.

===Direct page===
The zero page address mode was enhanced in several late model 8-bit processors, including the [[WDC 65816]], the [[CSG 65CE02]], and the [[Motorola 6809]]. The new mode, known as "direct page" addressing, added the ability to move the 256-byte zero page memory window from the start of memory (offset address $0000) to a new location within the first 64&nbsp;KB of memory.

The CSG 65CE02 allowed the direct page to be moved to any 256-byte boundary within the first 64&nbsp;KB of memory by storing an 8-bit offset value in the new base page (B) register. The Motorola 6809 could do the same with its direct page (DP) register. The WDC 65816 went a step further and allowed the direct page to be moved to any location within the first 64&nbsp;KB of memory by storing a 16-bit offset value in the new direct (D) register.

As a result, a greater number of programs were able to utilize the enhanced direct page addressing mode versus legacy processors that only included the zero page addressing mode.

===Scaled index with bounds checking===
This is similar to scaled index addressing, except that the instruction has two extra operands (typically constants), and the hardware checks that the index value is between these bounds.

Another variation uses vector descriptors to hold the bounds; this makes it easy to implement dynamically allocated arrays and still have full bounds checking.

===Indirect to bit field within word===
Some computers had special indirect addressing modes for subfields within words.

The [[GE-600 series|GE/Honeywell 600 series]] character addressing indirect word specified either 6-bit or 9-bit character fields within its [[36-bit computing|36-bit]] word.

The DEC [[PDP-10]], also 36-bit, had special instructions which allowed memory to be treated as a sequence of fixed-size bit fields or bytes of any size from 1 bit to 36 bits. A one-word sequence descriptor in memory, called a "byte pointer", held the current word address within the sequence, a bit position within a word, and the size of each byte.

Instructions existed to load and store bytes via this descriptor, and to increment the descriptor to point at the next byte (bytes were not split across word boundaries). Much DEC software used five 7-bit bytes per word (plain ASCII characters), with one bit per word unused. Implementations of [[C (programming language)|C]] had to use four 9-bit bytes per word, since the 'malloc' function in C assumes that the size of an ''int'' is some multiple of the size of a ''char'';<ref>[http://www.codingunit.com/c-reference-stdlib-h-function-malloc "C Reference: function malloc()"]</ref> the actual multiple is determined by the system-dependent compile-time operator [[sizeof]].

===Index next instruction===
The [[Elliott 503]],<ref name="brooks">Dave Brooks. [https://web.archive.org/web/20141101211113/http://members.iinet.com.au/~daveb/history.html#puzzle "Some Old Computers"].</ref> the [[Elliott 803]],<ref name="brooks"/><ref>Bill Purvis. [https://web.archive.org/web/20080616173228/http://bil.members.beeb.net/inst803.html "Some details of the Elliott 803B hardware"]</ref> and the [[Apollo Guidance Computer]] only used absolute addressing, and did not have any index registers.
Thus, indirect jumps, or jumps through registers, were not supported in the instruction set. Instead, it could be instructed to ''add the contents of the current memory word to the next instruction''. Adding a small value to the next instruction to be executed could, for example, change a <code>JUMP 0</code> into a <code>JUMP 20</code>, thus creating the effect of an indexed jump. Note that the instruction is modified on-the-fly and remains unchanged in memory, i.e. it is not [[self-modifying code]]. If the value being added to the next instruction was large enough, it could modify the opcode of that instruction as well as or instead of the address.