Editing Dynamic random-access memory (section)

====Principles of operation====
An asynchronous DRAM chip has power connections, some number of address inputs (typically 12), and a few (typically one or four) bidirectional data lines. There are three main [[active-low]] control signals:
* {{overline|RAS}}, the Row Address Strobe. The address inputs are captured on the falling edge of {{overline|RAS}}, and select a row to open. The row is held open as long as {{overline|RAS}} is low.
* {{overline|CAS}}, the Column Address Strobe. The address inputs are captured on the falling edge of {{overline|CAS}}, and select a column from the currently open row to read or write.
* {{overline|WE}}, Write Enable. This signal determines whether a given falling edge of {{overline|CAS}} is a read (if high) or write (if low). If low, the data inputs are also captured on the falling edge of {{overline|CAS}}.  If high, the data outputs are enabled by the falling edge of {{overline|CAS}} and produce valid output after the internal access time.

This interface provides direct control of internal timing: when {{overline|RAS}} is driven low, a {{overline|CAS}} cycle must not be attempted until the sense amplifiers have sensed the memory state, and {{overline|RAS}} must not be returned high until the storage cells have been refreshed. When {{overline|RAS}} is driven high, it must be held high long enough for precharging to complete.

Although the DRAM is asynchronous, the signals are typically generated by a clocked memory controller, which limits their timing to multiples of the controller's clock cycle.

For completeness, we mention two other control signals which are not essential to DRAM operation, but are provided for the convenience of systems using DRAM:
* {{overline|CS}}, Chip Select. When this is high, all other inputs are ignored.  This makes it easy to build an array of DRAM chips which share the same control signals.  Just as DRAM internally uses the word lines to select one row of storage cells connect to the shared bit lines and sense amplifiers, {{overline|CS}} is used to select one row of DRAM chips to connect to the shared control, address, and data lines.
* {{overline|OE}}, Output Enable. This is an additional signal that (if high) inhibits output on the data I/&zwj;O pins, while allowing all other operations to proceed normally.  In many applications, {{overline|OE}} can be permanently connected low (output enabled whenever {{overline|CS}}, {{overline|RAS}} and {{overline|CAS}} are low and {{overline|WE}} is high), but in high-speed applications, judicious use of {{overline|OE}} can prevent [[bus contention]] between two DRAM chips connected to the same data lines.  For example, it is possible to have two [[interleaved memory]] banks sharing the address and data lines, but each having their own {{overline|RAS}}, {{overline|CAS}}, {{overline|WE}} and {{overline|OE}} connections.  The memory controller can begin a read from the second bank while a read from the first bank is in progress, using the two {{overline|OE}} signals to only permit one result to appear on the data bus at a time.<!--There's also the Late Write or [[read–modify–write]] cycle where a read is changed to a write by a falling edge on /WE while /CAS remains low, which requires using /OE to drive the write data on the bus before the falling edge of /WE,<ref name=IBM96/>[https://classes.engineering.wustl.edu/cse260m/images/9/9e/MT4LC4M16R6.pdf] but that's rarely used in the real world.-->

=====RAS-only refresh=====
Classic asynchronous DRAM is refreshed by opening each row in turn.

The refresh cycles are distributed across the entire refresh interval in such a way that all rows are refreshed within the required interval. To refresh one row of the memory array using {{overline|RAS}} only refresh (ROR), the following steps must occur:
# The row address of the row to be refreshed must be applied at the address input pins.
# {{overline|RAS}} must switch from high to low. {{overline|CAS}} must remain high.<!--Refresh still works if there are /CAS accesses, it's just not "row-only" any more.-->
# At the end of the required amount of time, {{overline|RAS}} must return high.

This can be done by supplying a row address and pulsing {{overline|RAS}} low; it is not necessary to perform any {{overline|CAS}} cycles. An external counter is needed to iterate over the row addresses in turn.<ref name=IBM96>{{cite tech report |type=Application Note |title=Understanding DRAM Operation |url=http://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf|publisher=[[IBM]]|archive-url=https://web.archive.org/web/20170829153054/http://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf|archive-date=29 August 2017|date=December 1996}}</ref> In some designs, the CPU handled RAM refresh. The [[Zilog Z80]] is perhaps the best known example, as it has an internal row counter R which supplies the address for a special refresh cycle generated after each instruction fetch.<!--And data transfer in string instructions, and during HALT, but that's more detail than we need here.--><ref>{{cite tech report |title=Z80 CPU |type=User Manual |url=http://www.zilog.com/docs/z80/um0080.pdf#page=17 |page=3 |id=UM008011-0816 |year=2016}}</ref> In other systems, especially [[home computer]]s, refresh was handled by the video circuitry as a side effect of its periodic scan of the [[frame buffer]].<ref>{{cite web |url=https://retrocomputing.stackexchange.com/questions/14012/what-is-dram-refresh-and-why-is-the-weird-apple-ii-video-memory-layout-affected |title=What is DRAM refresh and why is the weird Apple II video memory layout affected by it? |date=3 March 2020}}</ref>

=====CAS before RAS refresh=====
For convenience, the counter was quickly incorporated into the DRAM chips themselves. If the {{overline|CAS}} line is driven low before {{overline|RAS}} (normally an illegal operation), then the DRAM ignores the address inputs and uses an internal counter to select the row to open.{{r|IBM96|TN-04-30}}  This is known as {{overline|CAS}}-before-{{overline|RAS}} (CBR) refresh. This became the standard form of refresh for asynchronous DRAM, and is the only form generally used with SDRAM.

=====Hidden refresh=====
Given support of {{overline|CAS}}-before-{{overline|RAS}} refresh, it is possible to deassert {{overline|RAS}} while holding {{overline|CAS}} low to maintain data output. If {{overline|RAS}} is then asserted again, this performs a CBR refresh cycle while the DRAM outputs remain valid. Because data output is not interrupted, this is known as ''hidden refresh''.<ref name=TN-04-30>{{cite tech report |type=Technical Note |title=Various Methods of DRAM Refresh |year=1994 |id=TN-04-30 |publisher=[[Micron Technology]] |url=http://www.downloads.reactivemicro.com/Public/Electronics/DRAM/DRAM%20Refresh.pdf |archive-url=https://web.archive.org/web/20111003001843/http://www.downloads.reactivemicro.com/Public/Electronics/DRAM/DRAM%20Refresh.pdf |archive-date=2011-10-03 |url-status=dead}}</ref>  Hidden refresh is no faster than a normal read followed by a normal refresh, but does maintain the data output valid during the refresh cycle.