Editing 3B series computers (section)

==Minicomputers==
===3B20S===
The 3B20S (simplex) was developed at [[Bell Labs]] and produced by Western Electric in 1982 for general purpose internal [[Bell System]] use. The 3B20S<ref name=3Bseries.NYT840328/> has hardware similar to the 3B20D, but one unit instead of two. The machine is approximately the size of a large [[refrigerator]], requiring a minimum of 170 square feet floor space.<ref>[http://bitsavers.trailing-edge.com/pdf/westernElectric/3b20s/234-301-910WE_3B20S_System_Index_and_Description_Jul81.pdf 3B20S Processor System Index and Description], Western Electric Co., July 1981.</ref> It was in use at the [[1984 Summer Olympics]], where around twelve 3B20S served the [[email]] requirements of the ''Electronic Messaging System'', which was built to replace the man-based messaging system of earlier Olympiads. The system connected around 1800 user terminals and 200 printers.<ref>{{cite journal
  |url=https://ieeexplore.ieee.org/document/1654251
  |title=Olympics electronic messaging system demonstrated
  |journal=[[IEEE Computer]] |volume=16 |issue=11 |date=November 1983  |page=113|doi = 10.1109/MC.1983.1654251|s2cid = 47105018|url-access=subscription}}</ref> The '''3B20A''' is an enhanced version of the 3B20S, adding in a second processing unit working in parallel as a multiprocessor unit.

===3B5===
The 3B5 is built with the older Western Electric [[Bellmac 32|WE 32000]] 32-bit microprocessor. The initial versions have discrete memory management unit hardware using gate arrays, and support segment-based memory translation.  I/O is programmed using memory-mapped techniques. The machine is approximately the size of a [[dishwasher]], though adding the reel-to-reel tape drive increases its size. These computers use [[Storage Module Device|SMD]] hard drives.

===3B15===
The 3B15, introduced in 1985,<ref name=unixreviewdec85>{{cite magazine |magazine=Unix Review |date=December 1985 |url=https://archive.org/details/Unix_Review_1985_Dec.pdf/page/n9/mode/1up |page=8 |title=The Monthly Report |last=Chandler |first=David}}</ref> uses the WE 32100 and is the faster follow-on to the 3B5 with similar large form factor.

===3B4000===
The 3B4000 is a [[high availability]] server introduced in 1987<ref>{{cite news |newspaper=[[The New York Times]]
|url=https://www.nytimes.com/1987/09/03/business/computers-introduced-at-at-t.html
|title=Computers Introduced At A.T.&T.
|author=Calvin Sims  |date=September 3, 1987}}</ref> and based on a 'snugly-coupled' architecture using the WE series 32x00 32-bit processor.  Known internally as 'Apache', the 3B4000 is a follow-on to the 3B15 and initial revisions use a 3B15 as a master processor.  Developed in the mid-1980's at the [[Lisle, Illinois|Lisle]] Indian Hill West facility by the High Performance Computer Development Lab, the system consists of multiple high performance (at the time) processor boards – adjunct processing elements (APEs) and adjunct communication elements (ACEs).  These adjunct processors run a customized UNIX kernel with drivers for SCSI (APEs) and serial boards (ACEs). The processing boards are interconnected by a redundant low latency parallel bus (ABUS) running at 20 MB/s. The UNIX kernels running on the adjunct processors are modified to allow the fork/exec of processes across processing units.  The system calls and peripheral drivers are also extended to allow processes to access remote resources across the ABUS.  Since the ABUS is hot-swappable, processors can be added or replaced without shutting down the system. If one of the adjunct processors fails during operation, the system can detect and restart programs that were running on the failed element.

The 3B4000 is capable of significant expansion; one test system (including storage) occupies 17 mid-height cabinets.  Generally, the performance of the system increases linearly with additional processing elements, however the lack of a true [[shared memory]] capability requires rewriting applications that rely heavily on this feature to avoid a severe performance penalty.