Editing AVR microcontrollers (section)

=== Basic families ===
AVRs are generally classified into following:

'''tinyAVR''' – the ATtiny series
{{Main|ATtiny microcontroller comparison chart}}

{| class="wikitable"
! [[Flash memory|Flash size]]
! Frequency<br />[MHz]
! [[Chip carrier|Package]]
! [[Static random-access memory|SRAM]]
! [[EEPROM]]
|- align="right"
| 0.5–32 KB
| 1.6–20
| 6–32-pin package
| 32–3072 bytes
| 64–512 bytes
|}

The ATtiny series features small package microcontrollers with a limited peripheral set available. However, the improved tinyAVR 0/1/2-series (released in 2016) include: 
* Peripherals equal to or exceed megaAVR 0-series
* Event System
* Improved AVRxt instruction set (improved timing of calls), hardware multiply

'''megaAVR''' – the ATmega series

{| class="wikitable"
! [[Flash memory|Flash size]]
! Frequency<br />[MHz]
! [[Chip carrier|Package]]
! [[Static random-access memory|SRAM]]
! [[EEPROM]]
|- align="right"
| 4–256 KB
| 1.6–20
| 28–100-pin package
| 256–16384 bytes
| 256–4096 bytes
|}

The ATmega series features microcontrollers that provide an extended instruction set (multiply instructions and instructions for handling larger program memories), an extensive peripheral set, a solid amount of program memory, as well as a wide range of pins available. The megaAVR 0-series (released in 2016) also has functionality such as: 
* Event system
* New peripherals with enhanced functionality
* Improved AVRxt instruction set (improved timing of calls)

'''AVR Dx''' – The AVR Dx family features multiple microcontroller series, focused on [[human–computer interaction|HCI]], analog signal conditioning and functional safety.

{| class="wikitable"
! [[Flash memory|Flash size]]
! Frequency<br />[MHz]
! [[Chip carrier|Package]]
! [[Static random-access memory|SRAM]]
! [[EEPROM]]
! Release year
|- align="right"
| 16–128 KB
| 20–24 at 1.8–5.5&nbsp;V
| 14–64-pin package
| 4–16 KB
| 512 bytes
| 2020
|}

The parts numbers is formatted as AVR''ff''D''xpp'', where ''ff'' is flash size, ''x'' is family, and ''pp'' is number of pins. Example: AVR128DA64 – 64-pin DA-series with 128k flash. All devices in the AVR Dx family include: 
* an Async Type D timer that can run faster than the CPU
* 12-bit ADC
* 10-bit DAC
* '''AVR DA-series''' (early 2020) – The high memory density makes these MCUs well suited for both wired and wireless communication-stack-intensive functions.
** integrated sensors for capacitative touch measurement ([[Human–computer interaction|HCI]])
** updated core independent peripherals ([[Autonomous peripheral operation|CIPs]]) and analog peripherals
** no external high frequency crystal
* '''AVR DB-series''' (mid-late 2020) – inherits many features from the DA-family, while adding its own:
** 2 or 3 on-chip opamps
** MultiVoltage IO (MVIO) on PORTC
** Supports external HF crystal
* '''AVR DD-series'''
** 16–64 KiB Flash
** 2–8 KiB SRAM
** 14–32-pin package
** internal 24&nbsp;MHz oscillator
** 7–23-channel 130 kS/s 12-bit differential Analog-to-Digital Converter (ADC)
** no amplifiers
** 1 analog comparator
** Two  USARTs, one SPI, one dual-mode TWI
** Multi-Voltage Input/Output (MVIO) support on 3 or 4 pins on Port C
** 4 Configurable Custom Logic (CCL) cells, 6 Event System channels
* '''AVR EA-series'''
** 8–64 KiB Flash
** 28–48-pin package
** internal 20&nbsp;MHz oscillator
** 24–32-channel 130 kS/s 12-bit differential Analog-to-Digital Converter (ADC)
** Programmable Gain Amplifier (PGA) with up to 16x gain
** 2 analog comparators
** Three USARTs, one SPI, one dual-mode TWI
** no Multi-Voltage Input/Output (MVIO)
** 4 Configurable Custom Logic (CCL) cells, 6 Event System channels

'''XMEGA'''

{| class="wikitable"
! [[Flash memory|Flash size]]
! Frequency<br />[MHz]
! [[Chip carrier|Package]]
! [[Static random-access memory|SRAM]]
! [[EEPROM]]
! Release year
|- align="right"
| 16–256 KB
| 32
| 44–100-pin package
| 1–32 KB
| 512–2048 bytes
| — 
|}

the ATxmega series offers a wide variety of peripherals and functionality such as:
* Extended performance features, such as DMA, "Event System", and cryptography support
* Extensive peripheral set with [[Analog-to-digital converter|ADCs]]

'''Application-specific AVR'''
* megaAVRs with special features not found on the other members of the AVR family, such as LCD controller, [[Universal Serial Bus|USB]] controller, advanced PWM, CAN, etc.

'''FPSLIC (AVR with FPGA)'''
* [[Field-programmable gate array|FPGA]] 5k to 40k gates
* SRAM for the AVR program code, unlike all other AVRs
* AVR core can run at up to 50&nbsp;MHz<ref>[http://www.atmel.com/products/other/field_programmable_gate_array/default.aspx Field Programmable System Level Integrated Circuit]. {{webarchive|url=https://web.archive.org/web/20121127102202/http://www.atmel.com/products/other/field_programmable_gate_array/default.aspx|date=2012-11-27}}.</ref>

'''32-bit AVRs'''{{Main|AVR32}}
* In 2006, Atmel released microcontrollers based on the 32-bit [[AVR32]] architecture. This was a completely different architecture unrelated to the 8-bit AVR, intended to compete with the [[ARM architecture|ARM]]-based processors. It had a 32-bit data path, [[SIMD]] and [[Digital signal processor|DSP]] instructions, along with other audio- and video-processing features. The instruction set was similar to other RISC cores, but it was not compatible with the original AVR (nor any of the various ARM cores). Since then support for AVR32 has been dropped from Linux as of kernel 4.12; compiler support for the architecture in [[GNU Compiler Collection|GCC]] was never mainlined into the compiler's central source-code repository and was available primarily in a vendor-supported fork. At the time that AVR32 was introduced, Atmel had already been a licensee of the [[ARM architecture]], with both [[ARM7]] and [[ARM9]] microcontrollers having been released prior to and concurrently with the AVR32; later Atmel focused most development effort on 32-bit chips with [[ARM Cortex-M]] and [[ARM Cortex-A|Cortex-A]] cores.