Editing Adder (electronics) (section)

===Half adder===
The '''half adder''' adds two single binary digits <math>A</math> and <math>B</math>. It has two outputs, sum (<math>S</math>) and carry (<math>C</math>). The carry signal represents an [[Integer overflow|overflow]] into the next digit of a multi-digit addition. The value of the sum is <math>2C + S</math>. The simplest half-adder design, pictured on the right, incorporates an [[XOR gate]] for <math>S</math> and an [[AND gate]] for <math>C</math>. The Boolean logic for the sum (in this case <math>S</math>) will be <math>A \oplus B</math> whereas for the carry (<math>C</math>) will be <math>A \cdot B</math>. With the addition of an [[OR gate]] to combine their carry outputs, two half adders can be combined to make a full adder.<ref name="Lancaster_2004"/>

The [[truth table]] for the half adder is:
:{| class="wikitable" style="text-align:center"
|- 
! colspan="2"| Inputs || colspan="2"| Outputs
|- style="background:#def; text-align:center;"
| '''A''' || '''B''' || '''C'''<sub>out</sub>  || '''S'''
|-
| {{no2|0}} || {{no2|0}} || {{no2|0}}  || {{no2|0}}
|-
| {{no2|0}} || {{yes2|1}} || {{no2|0}}  || {{yes2|1}}
|- 
| {{yes2|1}} || {{no2|0}} || {{no2|0}}  || {{yes2|1}}
|- 
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}}  || {{no2|0}}
|-
|}

Various half adder digital logic circuits:
<gallery widths="220px" heights="165px">
File:Halfadder.gif|Half adder in action.
File:half Adder.svg|[[Schematic]] of half adder implemented with one [[XOR gate]] and one [[AND gate]].
File:Half adder using NAND gates only.jpg|Schematic of half adder implemented with five [[NAND gate]]s.
File:1-bit half-adder.svg|[[Electronic symbol|Schematic symbol]] for a 1-bit half adder.
</gallery>