Editing Berkeley RISC (section)

==RISC II==

[[File:RISC-II Blue die shot.jpg|thumb|RISC II die shot]]
While the RISC I design ran into delays, work at Berkeley had already turned to the new ''Blue'' design. Work on Blue progressed slower than Gold, due both to the lack of a pressing need now that Gold was going to fab, and to changeovers in the classes and students staffing the effort. This pace also allowed them to add in several new features that would end up improving the design considerably.

The key difference was simpler cache circuitry that eliminated one line per bit (from three to two), dramatically shrinking the register file size. The change also required much tighter bus timing, but this was a small price to pay and in order to meet the needs several other parts of the design were sped up as well.

The savings due to the new design were tremendous. Whereas Gold contained a total of 78 registers in 6 windows, Blue contained 138 registers broken into 8 windows of 16 registers each, with another 10 globals. This expansion of the register file increases the chance that a given procedure can fit all of its local storage in registers, and increase the nesting depth. Nevertheless, the larger register file required fewer transistors, and the final Blue design, fabbed as ''RISC II'', implemented all of the RISC instruction set with only 40,760 transistors.<ref>{{Cite web|title=Berkeley Hardware Prototypes|url=https://people.eecs.berkeley.edu/~pattrsn/Arch/prototypes2.html|access-date=2021-11-06|website=people.eecs.berkeley.edu}}</ref>

The other major change was to include an ''instruction-format expander'', which invisibly "up-converted" 16-bit instructions into a 32-bit format.{{Citation needed|date=August 2023|reason=Not found in any available documentation on RISC II}}
This allowed smaller instructions, typically things with one or no operands, like <code>NOP</code>, to be stored in memory in a smaller 16-bit format, and for two such instructions to be packed into a single machine word. The instructions would be invisibly expanded back to 32-bit versions before they reached the [[arithmetic logic unit]] (ALU), meaning that no changes were needed in the core logic. This simple technique yielded a surprising 30% improvement in code density, making an otherwise identical program on Blue run faster than on Gold due to the decreased number of memory accesses.

RISC II proved to be much more successful in silicon and in testing outperformed almost all minicomputers on almost all tasks. For instance, performance ranged from 85% of VAX speed to 256% on a variety of loads. RISC II was also benched against the famous [[Motorola 68000]], then considered to be the best commercial chip implementation, and outperformed it by 140% to 420%.