Editing Bus error (section)

===Unaligned access===
Most CPUs are ''byte-addressable'', where each unique memory address refers to an 8-bit [[byte]]. Most CPUs can access individual bytes from each memory address, but they generally cannot access larger units (16 bits, 32 bits, 64 bits and so on) without these units being "[[Data structure alignment|aligned]]" to a specific boundary (the [[x86|x86 platform]] being a notable exception).

For example, if multi-byte accesses must be 16 bit-aligned, addresses (given in bytes) at 0, 2, 4, 6, and so on would be considered aligned and therefore accessible, while addresses 1, 3, 5, and so on would be considered unaligned. Similarly, if multi-byte accesses must be 32-bit aligned, addresses 0, 4, 8, 12, and so on would be considered aligned and therefore accessible, and all addresses in between would be considered unaligned. Attempting to access a unit larger than a byte at an unaligned address can cause a bus error.

Some systems may have a hybrid of these depending on the architecture being used. For example, for hardware based on the [[IBM System/360]] mainframe, including the [[IBM System z]], Fujitsu B8000, RCA Spectra, and [[UNIVAC Series 90]], instructions must be on a 16-bit boundary, that is, execution addresses must start on an even byte. Attempts to branch to an odd address results in a specification exception.<ref>''z/Architecture Principles of Operation'', SA22-7832-04, Page 6-6, Fifth Edition (September, 2005) IBM Corporation, Poukeepsie, NY, Retrievable from http://publibfp.dhe.ibm.com/epubs/pdf/a2278324.pdf {{Webarchive|url=https://web.archive.org/web/20220522015805/http://publibfp.dhe.ibm.com/epubs/pdf/a2278324.pdf |date=2022-05-22 }} (Retrieved December 31, 2015)</ref> Data, however, may be retrieved from any address in memory, and may be one byte or longer depending on the instruction.

CPUs generally access data at the full width of their [[bus (computing)|data bus]] at all times. To address bytes, they access memory at the full width of their data bus, then mask and shift to address the individual byte. Systems tolerate this inefficient algorithm, as it is an essential feature for most software, especially [[string (computer science)|string]] processing. Unlike bytes, larger units can span two aligned addresses and would thus require more than one fetch on the data bus.
It is possible for CPUs to support this, but this functionality is rarely required directly at the [[machine code]] level, thus CPU designers normally avoid implementing it and instead issue bus errors for unaligned memory access.