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CAS latency
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===Memory timing examples=== {| class="wikitable sortable" |+Memory timing examples (CAS latency only){{citation needed|date=July 2019|reason=I suspect the source of this table is from the Google Sheets Document in the external links below, which is self reported and therefore violates Wikipedia:No original research, and is unverifiable.}}{{Original research inline|date=December 2019}} ! scope="col" | Generation ! scope="col" | Type ! scope="col" data-sort-type="number" | Data rate ! scope="col" data-sort-type="number" | Transfer time{{Efn|Transfer time {{=}} 1 / Data rate.}} ! scope="col" data-sort-type="number" | Command rate{{Efn|Command rate {{=}} Data rate / 2 for double data rate (DDR), Command rate {{=}} Data rate for single data rate (SDR).}} ! scope="col" data-sort-type="number" | Cycle time{{Efn|Cycle time {{=}} 1 / Command rate {{=}} 2 Γ Transfer time.}} ! scope="col" | CAS latency ! scope="col" data-sort-type="number" | First word{{Efn|name="nthword"|''N''th word {{=}} [(2 Γ CAS latency) + (N β 1)] Γ Transfer time.}} ! scope="col" data-sort-type="number" | Fourth word{{Efn|name="nthword"}} ! scope="col" data-sort-type="number" | Eighth word{{Efn|name="nthword"}} |- ! scope="row" rowspan="2" | [[SDRAM]] <!-- The helper templates are DDR-specific, so compute SDR rows by hand --> | PC100 |align=right| 100 MT/s |align=right| 10.000 ns |align=right| 100 MHz |align=right| 10.000 ns |align=center| 2 |align=right| 20.00 ns |align=right| 50.00 ns |align=right| 90.00 ns |- | PC133 |align=right| 133 MT/s |align=right| 7.500 ns |align=right| 133 MHz |align=right| 7.500 ns |align=center| 3 |align=right| 22.50 ns |align=right| 45.00 ns |align=right| 75.00 ns |- ! scope="row" rowspan="4" | [[DDR SDRAM]] {{CAS latency/group|1|DDR|333|1}} {{CAS latency/row|333|1|2.5}} |- {{CAS latency/group|3|DDR|400|0}} {{CAS latency/row|400|0|3}} |- {{CAS latency/row|400|0|2.5}} |- {{CAS latency/row|400|0|2}} |- ! scope="row" rowspan="15" | [[DDR2 SDRAM]] {{CAS latency/group|2|DDR2|400|0}} {{CAS latency/row|400|0|4}} |- {{CAS latency/row|400|0|3}} |- {{CAS latency/group|2|DDR2|533|1}} {{CAS latency/row|533|1|4}} |- {{CAS latency/row|533|1|3}} |- {{CAS latency/group|2|DDR2|667|-1}} {{CAS latency/row|667|-1|5}} |- {{CAS latency/row|667|-1|4}} |- {{CAS latency/group|4|DDR2|800|0}} {{CAS latency/row|800|0|6}} |- {{CAS latency/row|800|0|5}} |- {{CAS latency/row|800|0|4.5}} |- {{CAS latency/row|800|0|4}} |- {{CAS latency/group|5|DDR2|1066|2}} {{CAS latency/row|1066|2|7}} |- {{CAS latency/row|1066|2|6}} |- {{CAS latency/row|1066|2|5}} |- {{CAS latency/row|1066|2|4.5}} |- {{CAS latency/row|1066|2|4}} |- ! scope="row" rowspan="41" | [[DDR3 SDRAM]] {{CAS latency/group|1|DDR3|1066|2}} {{CAS latency/row|1066|2|7}} |- {{CAS latency/group|4|DDR3|1333|1}} {{CAS latency/row|1333|1|9}} |- {{CAS latency/row|1333|1|8}} |- {{CAS latency/row|1333|1|7}} |- {{CAS latency/row|1333|1|6}} |- {{CAS latency/group|1|DDR3|1375|0}} {{CAS latency/row|1375|0|5}} |- {{CAS latency/group|6|DDR3|1600|0}} {{CAS latency/row|1600|0|11}} |- {{CAS latency/row|1600|0|10}} |- {{CAS latency/row|1600|0|9}} |- {{CAS latency/row|1600|0|8}} |- {{CAS latency/row|1600|0|7}} |- {{CAS latency/row|1600|0|6}} |- {{CAS latency/group|3|DDR3|1866|2}} {{CAS latency/row|1866|2|10}} |- {{CAS latency/row|1866|2|9}} |- {{CAS latency/row|1866|2|8}} |- {{CAS latency/group|1|DDR3|2000|0}} {{CAS latency/row|2000|0|9}} |- {{CAS latency/group|6|DDR3|2133|1}} {{CAS latency/row|2133|1|12}} |- {{CAS latency/row|2133|1|11}} |- {{CAS latency/row|2133|1|10}} |- {{CAS latency/row|2133|1|9}} |- {{CAS latency/row|2133|1|8}} |- {{CAS latency/row|2133|1|7}} |- {{CAS latency/group|1|DDR3|2200|0}} {{CAS latency/row|2200|0|7}} |- {{CAS latency/group|5|DDR3|2400|0}} {{CAS latency/row|2400|0|13}} |- {{CAS latency/row|2400|0|12}} |- {{CAS latency/row|2400|0|11}} |- {{CAS latency/row|2400|0|10}} |- {{CAS latency/row|2400|0|9}} |- {{CAS latency/group|1|DDR3|2600|0}} {{CAS latency/row|2600|0|11}} |- {{CAS latency/group|4|DDR3|2666|2}} {{CAS latency/row|2666|2|15}} |- {{CAS latency/row|2666|2|13}} |- {{CAS latency/row|2666|2|12}} |- {{CAS latency/row|2666|2|11}} |- {{CAS latency/group|3|DDR3|2800|0}} {{CAS latency/row|2800|0|16}} |- {{CAS latency/row|2800|0|12}} |- {{CAS latency/row|2800|0|11}} |- {{CAS latency/group|1|DDR3|2933|1}} {{CAS latency/row|2933|1|12}} |- {{CAS latency/group|1|DDR3|3000|0}} {{CAS latency/row|3000|0|12}} |- {{CAS latency/group|1|DDR3|3100|0}} {{CAS latency/row|3100|0|12}} |- {{CAS latency/group|1|DDR3|3200|0}} {{CAS latency/row|3200|0|16}} |- {{CAS latency/group|1|DDR3|3300|0}} {{CAS latency/row|3300|0|16}} |- ! scope="row" rowspan="63" | [[DDR4 SDRAM]] |- {{CAS latency/group|3|DDR4|1600|0}} {{CAS latency/row|1600|0|12}} |- {{CAS latency/row|1600|0|11}} |- {{CAS latency/row|1600|0|10}} |- {{CAS latency/group|3|DDR4|1866|2}} {{CAS latency/row|1866|2|14}} |- {{CAS latency/row|1866|2|13}} |- {{CAS latency/row|1866|2|12}} |- {{CAS latency/group|3|DDR4|2133|1}} {{CAS latency/row|2133|1|16}} |- {{CAS latency/row|2133|1|15}} |- {{CAS latency/row|2133|1|14}} |- {{CAS latency/group|3|DDR4|2400|0}} {{CAS latency/row|2400|0|17}} |- {{CAS latency/row|2400|0|16}} |- {{CAS latency/row|2400|0|15}} |- {{CAS latency/group|5|DDR4|2666|2}} {{CAS latency/row|2666|2|19}} |- {{CAS latency/row|2666|2|17}} |- {{CAS latency/row|2666|2|16}} |- {{CAS latency/row|2666|2|15}} |- {{CAS latency/row|2666|2|13}} |- {{CAS latency/group|4|DDR4|2800|0}} {{CAS latency/row|2800|0|17}} |- {{CAS latency/row|2800|0|16}} |- {{CAS latency/row|2800|0|15}} |- {{CAS latency/row|2800|0|14}} |- {{CAS latency/group|4|DDR4|3000|0}} {{CAS latency/row|3000|0|17}} |- {{CAS latency/row|3000|0|16}} |- {{CAS latency/row|3000|0|15}} |- {{CAS latency/row|3000|0|14}} |- {{CAS latency/group|3|DDR4|3200|0}} {{CAS latency/row|3200|0|16}} |- {{CAS latency/row|3200|0|15}} |- {{CAS latency/row|3200|0|14}} |- {{CAS latency/group|1|DDR4|3300|0}} {{CAS latency/row|3300|0|16}} |- {{CAS latency/group|1|DDR4|3333|1}} {{CAS latency/row|3333|1|16}} |- {{CAS latency/group|2|DDR4|3400|0}} {{CAS latency/row|3400|0|16}} |- {{CAS latency/row|3400|0|14}} |- {{CAS latency/group|3|DDR4|3466|2}} {{CAS latency/row|3466|2|18}} |- {{CAS latency/row|3466|2|17}} |- {{CAS latency/row|3466|2|16}} |- {{CAS latency/group|2|DDR4|3533|0}} {{CAS latency/row|3533|0|16}} |- {{CAS latency/row|3533|0|15}} |- {{CAS latency/group|6|DDR4|3600|0}} {{CAS latency/row|3600|0|19}} |- {{CAS latency/row|3600|0|18}} |- {{CAS latency/row|3600|0|17}} |- {{CAS latency/row|3600|0|16}} |- {{CAS latency/row|3600|0|15}} |- {{CAS latency/row|3600|0|14}} |- {{CAS latency/group|1|DDR4|3733|1}} {{CAS latency/row|3733|1|17}} |- {{CAS latency/group|1|DDR4|3866|2}} {{CAS latency/row|3866|2|18}} |- {{CAS latency/group|4|DDR4|4000|0}} {{CAS latency/row|4000|0|19}} |- {{CAS latency/row|4000|0|18}} |- {{CAS latency/row|4000|0|17}} |- {{CAS latency/row|4000|0|16}} |- {{CAS latency/group|1|DDR4|4133|1}} {{CAS latency/row|4133|1|19}} |- {{CAS latency/group|1|DDR4|4200|0}} {{CAS latency/row|4200|0|19}} |- {{CAS latency/group|4|DDR4|4266|2}} {{CAS latency/row|4266|2|19}} |- {{CAS latency/row|4266|2|18}} |- {{CAS latency/row|4266|2|17}} |- {{CAS latency/row|4266|2|16}} |- {{CAS latency/group|3|DDR4|4400|2}} {{CAS latency/row|4400|2|19}} |- {{CAS latency/row|4400|2|18}} |- {{CAS latency/row|4400|2|17}} |- {{CAS latency/group|2|DDR4|4600|2}} {{CAS latency/row|4600|2|19}} |- {{CAS latency/row|4600|2|18}} |- {{CAS latency/group|2|DDR4|4800|0}} {{CAS latency/row|4800|0|20}} |- {{CAS latency/row|4800|0|19}} |- ! scope="row" rowspan="33" | [[DDR5 SDRAM]] |- {{CAS latency/group|4|DDR5|4800|0}} {{CAS latency/row|4800|0|40}} |- {{CAS latency/row|4800|0|38}} |- {{CAS latency/row|4800|0|36}} |- {{CAS latency/row|4800|0|34}} |- {{CAS latency/group|4|DDR5|5200|0}} {{CAS latency/row|5200|0|40}} |- {{CAS latency/row|5200|0|38}} |- {{CAS latency/row|5200|0|36}} |- {{CAS latency/row|5200|0|34}} |- {{CAS latency/group|6|DDR5|5600|0}} {{CAS latency/row|5600|0|40}} |- {{CAS latency/row|5600|0|38}} |- {{CAS latency/row|5600|0|36}} |- {{CAS latency/row|5600|0|34}} |- {{CAS latency/row|5600|0|30}} |- {{CAS latency/row|5600|0|28}} |- {{CAS latency/group|5|DDR5|6000|0}} {{CAS latency/row|6000|0|40}} |- {{CAS latency/row|6000|0|38}} |- {{CAS latency/row|6000|0|36}} |- {{CAS latency/row|6000|0|32}} |- {{CAS latency/row|6000|0|30}} |- {{CAS latency/group|3|DDR5|6200|0}} {{CAS latency/row|6200|0|40}} |- {{CAS latency/row|6200|0|38}} |- {{CAS latency/row|6200|0|36}} |- {{CAS latency/group|5|DDR5|6400|0}} {{CAS latency/row|6400|0|40}} |- {{CAS latency/row|6400|0|38}} |- {{CAS latency/row|6400|0|36}} |- {{CAS latency/row|6400|0|34}} |- {{CAS latency/row|6400|0|32}} |- {{CAS latency/group|1|DDR5|6600|0}} {{CAS latency/row|6600|0|34}} |- {{CAS latency/group|1|DDR5|6800|0}} {{CAS latency/row|6800|0|34}} |- {{CAS latency/group|2|DDR5|7200|0}} {{CAS latency/row|7200|0|36}} |- {{CAS latency/row|7200|0|34}} |- {{CAS latency/group|1|DDR5|7600|0}} {{CAS latency/row|7600|0|38}} |- ! scope="col" | Generation ! scope="col" | Type ! scope="col" | Data rate ! scope="col" | Transfer time ! scope="col" | Command rate ! scope="col" | Cycle time ! scope="col" | CAS latency ! scope="col" | First word ! scope="col" | Fourth word ! scope="col" | Eighth word |} ====Notes==== {{Noteslist}}
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