Editing CMOS (section)

== Inversion ==
CMOS circuits are constructed in such a way that all [[PMOS logic|P-type metal–oxide–semiconductor]] (PMOS) transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all [[NMOS logic|NMOS]] transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low [[Electrical resistance|resistance]] between its source and drain contacts when a low gate [[voltage]] is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct, while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time, both pMOS and nMOS MOSFETs conduct briefly as the gate voltage transitions from one state to another. This induces a brief spike in power consumption and becomes a serious issue at high frequencies.

[[File:CMOS Inverter.svg|thumb|Static CMOS inverter. '''V<sub>dd</sub>''' and '''V<sub>ss</sub>''' stand for [[IC power-supply pin|drain and source]], respectively.{{Efn|Transistors symbols show here are simplified logic symbols and not electrical schematic symbols.}}]]
The adjacent image shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). Vdd is some positive voltage connected to a power supply and Vss is ground. A is the input and Q is the output.

When the voltage of A is low (i.e. close to Vss), the NMOS transistor's channel is in a high resistance state, disconnecting Vss from Q. The PMOS transistor's channel is in a low resistance state, connecting Vdd to Q. Q, therefore, registers Vdd.

On the other hand, when the voltage of A is high (i.e. close to Vdd), the PMOS transistor is in a high resistance state, disconnecting Vdd from Q. The NMOS transistor is in a low resistance state, connecting Vss to Q. Now, Q registers Vss.

In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. No matter what the input is, the output is never left floating (charge is never stored due to wire capacitance and lack of electrical drain/ground). Because of this behavior of input and output, the CMOS circuit's output is the inverse of the input.

The transistors' resistances are never exactly equal to zero or infinity, so Q will never exactly equal Vss or Vdd, but Q will always be closer to Vss than A was to Vdd (or vice versa if A were close to Vss). Without this amplification, there would be a very low limit to the number of logic gates that could be chained together in series, and CMOS logic with billions of transistors would be impossible.

=== Power supply pins ===
{{See also|IC power-supply pin}}
The power supply pins for CMOS are called V<sub>DD</sub> and V<sub>SS</sub>, or V<sub>CC</sub> and Ground(GND) depending on the manufacturer. V<sub>DD</sub> and V<sub>SS</sub> are carryovers from conventional MOS circuits and stand for the ''drain'' and ''source'' supplies.<ref>{{cite web |url=http://www.fairchildsemi.com/an/AN/AN-77.pdf |title=CMOS, the Ideal Logic Family |publisher=Fairchild Semiconductor |date=January 1983 |access-date=2011-11-25 |url-status=dead |archive-url=https://web.archive.org/web/20111209004748/http://www.fairchildsemi.com/an/AN/AN-77.pdf |archive-date=2011-12-09 }}</ref> These do not apply directly to CMOS, since both supplies are really source supplies. V<sub>CC</sub> and Ground are carryovers from [[TTL logic]] and that nomenclature has been retained with the introduction of the 54C/74C line of CMOS.

=== Duality ===
An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be the [[Complement (set theory)#Logical complement|complement]] of the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the logic based on [[De Morgan's laws]], the PMOS transistors in parallel have corresponding NMOS transistors in series while the PMOS transistors in series have corresponding NMOS transistors in parallel.

=== Logic ===
[[File:CMOS NAND.svg|thumb|upright|[[NAND gate]] in CMOS logic.{{Efn|Transistors symbols show here are simplified logic symbols and not electrical schematic symbols.}}]]

More complex logic functions such as those involving [[AND gate|AND]] and [[OR gate]]s require manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, both transistors must have low resistance to the corresponding supply voltage, modelling an AND. When a path consists of two transistors in parallel, either one or both of the transistors must have low resistance to connect the supply voltage to the output, modelling an OR.

Shown on the right is a [[circuit diagram]] of a [[NAND gate]] in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and ''V''<sub>ss</sub> (ground), bringing the output low. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and ''V''<sub>dd</sub> (voltage source), bringing the output high.  If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and ''V''<sub>dd</sub> (voltage source), bringing the output high.  As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a [[NAND gate|NAND]] (NOT AND) logic gate.

An advantage of CMOS over NMOS logic is that both low-to-high and high-to-low output transitions are fast since the (PMOS) pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full [[voltage]] between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

See [[Logical effort]] for a method of calculating delay in a CMOS circuit.

=== Example: NAND gate in physical layout ===
[[File:CMOS NAND Layout.svg|thumb|upright|The [[physical layout]] of a NAND circuit. The larger regions of N-type diffusion and P-type diffusion are part of the transistors. The two smaller regions on the left are taps to prevent [[latchup]]. ]]
[[File:CMOS fabrication process.svg|thumb|upright|Simplified process of fabrication of a CMOS inverter on p-type substrate in semiconductor microfabrication. In step 1, [[silicon dioxide]] layers are formed initially through [[thermal oxidation]] Note: Gate, source and drain contacts are not normally in the same plane in real devices, and the diagram is not to scale.]]

This example shows a [[Logical NAND|NAND]] logic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on a [[Extrinsic semiconductor#P-type semiconductors|P-type]] substrate. The [[polysilicon]], diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the P-type substrate. (See steps 1 to 6 in the process diagram below right) The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection.

The inputs to the [[NAND gate|NAND]] (illustrated in green color) are in polysilicon. The transistors (devices) are formed by the intersection of the polysilicon and diffusion; N diffusion for the N device & P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ("out") is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares). The [[physical layout]] example matches the NAND logic circuit given in the previous example.

The N device is manufactured on a P-type substrate while the P device is manufactured in an [[Extrinsic semiconductor#N-type semiconductors|N-type]] well (n-well). A P-type substrate "tap" is connected to V<sub>SS</sub> and an N-type n-well tap is connected to V<sub>DD</sub> to prevent [[latchup]].

[[Image:Cmos impurity profile-en.svg|center|thumbnail|500px|Cross section of two transistors in a CMOS gate, in an N-well CMOS process]]