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== Instruction set == COP8 operands are listed in destination, source order. Most instructions have the accumulator A as one of the operands. The other operand is generally chosen from an 8-bit immediate value, an 8-bit RAM address, or {{code|[B]}}, the RAM address selected by the B register. The {{code|LD}} and {{code|X}} (exchange with accumulator) instructions also support RAM addressing by the X register ({{code|[X]}}) and post-inc/decrement variants ({{code|[B+]}}, {{code|[Bβ]}}, {{code|[X+]}}, {{code|[Xβ]}}). Indirect addressing via B is particularly fast, and can be done in the same cycle that the instruction is executed; even {{code|X A,[B]}} is a one-cycle instruction. On the other hand, absolute RAM addressing is only directly encoded for five instructions: <code>LD A,''addr8''</code>, <code>X A,''addr8''</code>, <code>IFEQ ''addr8'',#''imm8''</code>, <code>LD ''addr8'',#''imm8''</code>, and [[#DIR|<code>DIR ''addr8''</code>]].<!--JSRB takes a ROM address--> The latter is a "direct addressing" prefix opcode which may be prepended to any instruction with a {{code|[B]}} operand, and changes the operand to the specified memory location. (Conditional-skip instructions skip the prefix and following instruction as a pair.) Using {{code|DIR}} with the {{code|LD A,[B]}}, {{code|X A,[B]}} and <code>LD [B],#''imm8''</code> instructions is not documented, as the dedicated instructions are more efficient. All "move" instructions are called {{code|LD}} (load) even if the destination is a memory address (<code>LD ''addr8'',#''imm8''</code>). Unusually, there are no {{code|LD}} instructions with the accumulator as a source; stores must be done with the {{code|X}} instruction which ''exchanges'' the accumulator with the memory operand, storing A and loading the previous memory contents. There are instructions to fetch from tables in ROM. These combine the high 7 bits of the program counter (PCU) with the accumulator, fetch a byte from that address, and place it in the accumulator ({{code|LAID}} instruction) or the low 8 bits of the program counter PCL ({{code|JID}} instruction). Because the next instruction executed must be in the same 256-byte page of ROM as the table itself, a 256-entry table is not possible. {|class="wikitable" style="text-align:center" |+ COP8 family instruction set<ref name=basic>{{cite book |title=COP8 Basic Family User's Manual |version=Revision 002 |date=June 1996 |id=Literature Number 620895-002 |publisher=[[National Semiconductor]] |url=http://bitsavers.org/components/national/_dataBooks/1996_National_COP8_Basic_Family_Users_Manual.pdf |access-date=2021-01-02}}</ref><ref name=feature>{{cite book |title=COP8 Feature Family User's Manual |version=Revision 005 |date=March 1999 |id=Literature Number 620897-005 |publisher=[[National Semiconductor]]}} Extracted from [[ZIP (file format)|zipped]] [[ISO image]] [http://bitsavers.informatik.uni-stuttgart.de/components/national/cop8/cdrom/530094-003_COP8_Tools_Docs_Aug1999.zip 530094-003_COP8_Tools_Docs_Aug1999.zip], retrieved 2020-01-07.</ref><ref name=comparison>{{cite web |title=Comparison of COP878x to the Enhanced COP8SAx7 Family - Hardware/Software Considerations |first=Abdul |last=Aleaf |publisher=[[National Semiconductor]] |date=July 1996 |id=Application Note 1043 |url=https://www.ti.com/lit/an/snoa378/snoa378.pdf}}</ref><ref>{{cite web |title=COP8SAx Designer's Guide |id=Literature Number 620894-001 |date=January 1997 |publisher=[[National Semiconductor]] |url=http://datasheet.elcodis.com/pdf/12/40/124000/dm-cop820d.pdf}}</ref> !colspan=8| Opcode ||colspan=2| Operands ||rowspan=2| Mnemonic || rowspan=2| Cycles ||rowspan=2| Description |- ! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 |- | 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || — || — ||align=left| INTR || 7 ||align=left| Software interrupt (push PC, PC β 0x00ff) |- | 0 || 0 || 0 ||colspan=5| ''offset'' || — || — ||align=left| JP +''disp5'' || 3 ||align=left| PC β PC + ''offset''; jump 1–31 bytes forward (offsetβ 0) |- | 0 || 0 || 1 || 0 ||colspan=4| ''high'' || ''low'' || — ||align=left| JMP ''addr12'' || 3 ||align=left| PC[11:0] β ''addr''. Top 3 bits of PC preserved. |- | 0 || 0 || 1 || 1 ||colspan=4| ''high'' || ''low'' || — ||align=left| JSR ''addr12'' || 5 ||align=left| Jump to subroutine: push PC, proceed as JMP. |- | 0 || 1 || 0 || 0 ||colspan=4| ''k'' || — || — ||align=left| IFBNE #''imm4'' || 1 ||align=left| Skip next instruction if (B & 15) = ''k''. |- | 0 || 1 || 0 || 1 ||colspan=4| ''k'' || — || — ||align=left| LD B,#''imm4'' || 1 ||align=left| B β 15 β ''k'' (zero-extended) |- |colspan=13| |- ! 0 || 1 || 1 || 0 || 0 ||colspan=3| ''opcode'' || || — ||colspan=3| Miscellaneous instructions |- | 0 || 1 || 1 || 0 || 0 || 0 || 0 || 0 || ''k'' || — ||align=left| ANDSZ A,#''imm8''{{efn|name=feature}} || 2 ||align=left| Skip if A & ''k'' = 0 (=IFBIT #''bit'',A) |- | 0 || 1 || 1 || 0 || 0 || 0 || 0 || 1 || ''addr'' || — ||align=left| JSRB ''addr8''{{efn|name=flash}} || 5 ||align=left| Push PC, jump to boot ROM subroutine at address<ref name=cop8s>{{cite web |title=COP8SBR9/COP8SCR9/COP8SDR98-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout |type=data sheet |date=April 2002 |publisher=[[National Semiconductor]] |url=http://radio-hobby.org/uploads/datasheet/39/cop8/cop8sdr9.pdf |accessdate=2021-01-06}}</ref><!--See also cop8cdr9.pdf--> |- style="background:lightgrey;" | 0 || 1 || 1 || 0 || 0 || 0 || 1 || – || — || — ||colspan=3 align=left| ''(reserved for boot ROM)''{{efn|name=flash}}{{r|cop8s}}<!--One instruction is RETF to return from boot ROM to flash. Not sure what the other is. JSRBL?--> |- | 0 || 1 || 1 || 0 || 0 || 1 || 0 || 0 || — || — ||align=left| CLR A || 1 ||align=left| A β 0 |- | 0 || 1 || 1 || 0 || 0 || 1 || 0 || 1 || — || — ||align=left| SWAP A || 1 ||align=left| A β A<<4 {{pipe}} A>>4; swap nibbles |- | 0 || 1 || 1 || 0 || 0 || 1 || 1 || 0 || — || — ||align=left| DCOR A || 1 ||align=left| Decimal correct after [[Binary-coded decimal|BCD]] addition |- | 0 || 1 || 1 || 0 || 0 || 1 || 1 || 1 || — || — ||align=left| PUSH A{{efn|name=feature}} || 3 ||align=left| [SP] β A, SP β SPβ1 |- |colspan=12| |- ! 0 || 1 || 1 ||colspan=2| ''opc'' ||colspan=3| ''bit'' || — || — ||colspan=3| Bit operations on [B]{{efn|name=dir}} |- | 0 || 1 || 1 || 0 || 1 ||colspan=3| ''bit'' || — || — ||align=left| RBIT #''bit'',[B]{{efn|name=dir}} || 1 ||align=left| Reset (clear to 0) given bit of RAM |- | 0 || 1 || 1 || 1 || 0 ||colspan=3| ''bit'' || — || — ||align=left| IFBIT #''bit'',[B]{{efn|name=dir}} || 1 ||align=left| Test given bit of RAM, skip if zero |- | 0 || 1 || 1 || 1 || 1 ||colspan=3| ''bit'' || — || — ||align=left| SBIT #''bit'',[B]{{efn|name=dir}} || 1 ||align=left| Set (to 1) given bit of RAM |- |colspan=12| |- ! 1 || 0 || 0 || ''m'' || 0 ||colspan=3| ''opcode'' || ''k?'' || — ||colspan=3| Binary operations, A β A op ''operand'' |- | 1 || 0 || 0 || 0 || 0 ||colspan=3| ''opcode'' || — || — ||align=left| ''OP'' A,[B]{{efn|name=dir}} || 1 ||align=left| A β A op [B] |- | 1 || 0 || 0 || 1 || 0 ||colspan=3| ''opcode'' || ''k'' || — ||align=left| ''OP'' A,#''imm8'' || 2 ||align=left| A β A op ''k'' |- | 1 || 0 || 0 || ''m'' || 0 || 0 || 0 || 0 || ''k?'' || — ||align=left| ADC A,''operand'' || ||align=left| C,A β A + ''operand'' + C; add with carry |- | 1 || 0 || 0 || ''m'' || 0 || 0 || 0 || 1 || ''k?'' || — ||align=left| SUBC A,''operand'' || ||align=left| C,A β A + ~''operand'' + C (A β ''operand'' β ~C) |- | 1 || 0 || 0 || ''m'' || 0 || 0 || 1 || 0 || ''k?'' || — ||align=left| IFEQ A,''operand'' || ||align=left| Skip if A β ''operand'' |- | 1 || 0 || 0 || ''m'' || 0 || 0 || 1 || 1 || ''k?'' || — ||align=left| IFGT A,''operand'' || ||align=left| Skip if A β€ ''operand'' |- | 1 || 0 || 0 || ''m'' || 0 || 1 || 0 || 0 || ''k?'' || — ||align=left| ADD A,''operand'' || ||align=left| A β A + ''operand'' (carry unchanged!) |- | 1 || 0 || 0 || ''m'' || 0 || 1 || 0 || 1 || ''k?'' || — ||align=left| AND A,''operand'' || ||align=left| A β A & ''operand'' |- | 1 || 0 || 0 || ''m'' || 0 || 1 || 1 || 0 || ''k?'' || — ||align=left| XOR A,''operand'' || ||align=left| A β A ^ ''operand'' |- | 1 || 0 || 0 || ''m'' || 0 || 1 || 1 || 1 || ''k?'' || — ||align=left| OR A,''operand'' || ||align=left| A β A {{pipe}} ''operand'' |- |colspan=13| |- ! 1 || 0 || 0 || 0 || 1 ||colspan=3| ''opcode'' || — || — ||colspan=3| Zero-operand instructions |- | 1 || 0 || 0 || 0 || 1 || 0 || 0 || 0 || — || — ||align=left| IFC || 1 ||align=left| Skip if carry clear |- | 1 || 0 || 0 || 0 || 1 || 0 || 0 || 1 || — || — ||align=left| IFNC || 1 ||align=left| Skip if carry set |- | 1 || 0 || 0 || 0 || 1 || 0 || 1 || 0 || — || — ||align=left| INC A || 1 ||align=left| A β A + 1 (carry unchanged) |- | 1 || 0 || 0 || 0 || 1 || 0 || 1 || 1 || — || — ||align=left| DEC A || 1 ||align=left| A β A β 1 (carry unchanged) |- | 1 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || — || — ||align=left| POP A{{efn|name=feature}} || 3 ||align=left| SP β SP+1, A β [SP] |- | 1 || 0 || 0 || 0 || 1 || 1 || 0 || 1 || — || — ||align=left| RETSK || 5 ||align=left| Pop PC, skip one instruction |- | 1 || 0 || 0 || 0 || 1 || 1 || 1 || 0 || — || — ||align=left| RET || 5 ||align=left| Pop PC high, pop PC low |- | 1 || 0 || 0 || 0 || 1 || 1 || 1 || 1 || — || — ||align=left| RETI || 5 ||align=left| Return and enable interrupts |- |colspan=13| |- ! 1 || 0 || 0 || 1 || 1 ||colspan=3| ''opcode'' || ''k'' || — ||colspan=3| Instructions with immediate operand |- | 1 || 0 || 0 || 1 || 1 || 0 || 0 || 0 || ''k'' || — ||align=left| LD A,#''imm8'' || 2 ||align=left| A β ''k'' |- | 1 || 0 || 0 || 1 || 1 || 0 || 0 || 1 || ''k'' || — ||align=left| IFNE A,#''imm8''{{efn|name=feature}} || 2 ||align=left| Skip if A = ''k'' |- | 1 || 0 || 0 || 1 || 1 || 0 || 1 || 0 || ''k'' || — ||align=left| LD [B+],#''imm8'' || 3 ||align=left| [B] β ''k'', B β B + 1 |- | 1 || 0 || 0 || 1 || 1 || 0 || 1 || 1 || ''k'' || — ||align=left| LD [Bβ],#''imm8'' || 3 ||align=left| [B] β ''k'', B β B β 1 |- | 1 || 0 || 0 || 1 || 1 || 1 || 0 || 0 || ''addr'' || — ||align=left| X A,''addr8'' || 3 ||align=left| A β [''addr''], exchange |- | 1 || 0 || 0 || 1 || 1 || 1 || 0 || 1 || ''addr'' || — ||align=left| LD A,''addr8'' || 3 ||align=left| A β [''addr''] |- | 1 || 0 || 0 || 1 || 1 || 1 || 1 || 0 || ''k'' || — ||align=left| LD [B],#''imm8'' || 2 ||align=left| [B] β ''k'' |- | 1 || 0 || 0 || 1 || 1 || 1 || 1 || 1 || ''k'' || — ||align=left| LD B,#''imm8''{{efn|name=feature}} || 2 ||align=left| B β ''k'' (=LD R14,#''k'', one cycle faster) |- |colspan=13| |- ! 1 || 0 || 1 ||colspan=3| ''opcode'' || 0 || ''c'' || || ||colspan=3| Miscellaneous instructions |- | 1 || 0 || 1 || 0 || 0 || 0 || 0 || 0 || — || — ||align=left| RC || 1 ||align=left| C β 0; reset carry to 0 |- | 1 || 0 || 1 || 0 || 0 || 0 || 0 || 1 || — || — ||align=left| SC || 1 ||align=left| C β 1; set carry to 1 |- | 1 || 0 || 1 || 0 || 0 || 1 || 0 || 0 || — || — ||align=left| LAID || 3 ||align=left| A β ROM[PCU:A]; load from ROM |- | 1 || 0 || 1 || 0 || 0 || 1 || 0 || 1 || — || — ||align=left| JID || 3 ||align=left| PCL β ROM[PCU:A]; jump via ROM table |- | 1 || 0 || 1 || 0 || 1 || 0 || 0 || 0 || — || — ||align=left| RLC A{{efn|name=feature}} || 1 ||align=left| C,A β A,C; rotate left through carry (=ADC A,A) |- | 1 || 0 || 1 || 0 || 1 || 0 || 0 || 1 || ''addr'' || ''k'' ||align=left| IFEQ ''addr8'',#''imm8''{{efn|name=feature}} || 3 ||align=left| Skip if [''addr''] β ''k'' |- | 1 || 0 || 1 || 0 || 1 || 1 || 0 || 0 || ''high'' || ''low'' ||align=left| JMPL ''addr15'' || 4 ||align=left| PC β ''address'' |- | 1 || 0 || 1 || 0 || 1 || 1 || 0 || 1 || ''high'' || ''low'' ||align=left| JSRL ''addr15'' || 5 ||align=left| Push PC, PC β ''address'' |- | 1 || 0 || 1 || 1 || 0 || 0 || 0 || 0 || — || — ||align=left| RRC A || 1 ||align=left| A,C β C,A; rotate right through carry |- style="background:lightgrey;" | 1 || 0 || 1 || 1 || 0 || 0 || 0 || 1 || — || — ||colspan=3 align=left| ''(reserved)'' |- | 1 || 0 || 1 || 1 || 0 || 1 || 0 || 0 || — || — ||align=left| VIS{{efn|name=feature}} || 5 ||align=left| PC β ROM[''vector table'']; Vector Interrupt Select |- | 1 || 0 || 1 || 1 || 0 || 1 || 0 || 1 || — || — ||align=left| RPND{{efn|name=feature}} || 1 ||align=left| Reset pending interrupt flag |- | 1 || 0 || 1 || 1 || 1 || 0 || 0 || 0 || — || — ||align=left| NOP || 1 ||align=left| No operation |- | 1 || 0 || 1 || 1 || 1 || 0 || 0 || 1 || — || — ||align=left| IFNE A,[B]{{efn|name=feature}}{{efn|name=dir}} || 1 ||align=left| Skip if A = [B] |- | 1 || 0 || 1 || 1 || 1 || 1 || 0 || 0 || ''addr'' || ''k'' ||align=left| LD ''addr8'',#''imm8'' || 3 ||align=left| [''addr''] β ''k'' |- | 1 || 0 || 1 || 1 || 1 || 1 || 0 || 1 || ''addr'' || — ||align=left| {{Anchor|DIR}}DIR ''addr8'' || 3 ||align=left| Change next instruction's operand from [B] to [''addr''] |- |colspan=13| |- ! 1 || 0 || 1 || ''R'' || ''L'' || ''='' || 1 || ''Β±'' || — || — ||colspan=3| Load/exchange operations |- | 1 || 0 || 1 || 0 || 0 || 0 || 1 || 0 || — || — ||align=left| X A,[B+] || 2 ||align=left| A β [B], B β B+1 |- | 1 || 0 || 1 || 0 || 0 || 0 || 1 || 1 || — || — ||align=left| X A,[Bβ] || 2 ||align=left| A β [B], B β Bβ1 |- | 1 || 0 || 1 || 0 || 0 || 1 || 1 || 0 || — || — ||align=left| X A,[B] || 1 ||align=left| A β [B] |- | 1 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || — || — ||align=left| LD A,[B+] || 2 ||align=left| A β [B], B β B+1 |- | 1 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || — || — ||align=left| LD A,[Bβ] || 2 ||align=left| A β [B], B β Bβ1 |- | 1 || 0 || 1 || 0 || 1 || 1 || 1 || 0 || — || — ||align=left| LD A,[B] || 1 ||align=left| A β [B] |- | 1 || 0 || 1 || 1 || 0 || 0 || 1 || 0 || — || — ||align=left| X A,[X+] || 3 ||align=left| A β [X], X β X+1 |- | 1 || 0 || 1 || 1 || 0 || 0 || 1 || 1 || — || — ||align=left| X A,[Xβ] || 3 ||align=left| A β [X], X β Xβ1 |- | 1 || 0 || 1 || 1 || 0 || 1 || 1 || 0 || — || — ||align=left| X A,[X] || 3 ||align=left| A β [X] |- | 1 || 0 || 1 || 1 || 1 || 0 || 1 || 0 || — || — ||align=left| LD A,[X+] || 3 ||align=left| A β [X], X β X+1 |- | 1 || 0 || 1 || 1 || 1 || 0 || 1 || 1 || — || — ||align=left| LD A,[Xβ] || 3 ||align=left| A β [X], X β Xβ1 |- | 1 || 0 || 1 || 1 || 1 || 1 || 1 || 0 || — || — ||align=left| LD A,[X] || 3 ||align=left| A β [X] |- style="background:lightgrey;" | 1 || 0 || 1 ||colspan=2| — || 1 || 1 || 1 || — || — ||colspan=3 align=left| ''(reserved)'' |- |colspan=13| |- | 1 || 1 || 0 || 0 ||colspan=4| ''register'' || — || — ||align=left| DRSZ ''register'' || 3 ||align=left| ''register'' β ''register'' β 1, skip if result is zero |- | 1 || 1 || 0 || 1 ||colspan=4| ''register'' || ''k'' || — ||align=left| LD ''register'',#''imm8'' || 3 ||align=left| ''register'' β ''k'' (=LD 0xf0+''register'',#''k'', one byte shorter) |- | 1 || 1 || 1 ||colspan=5| ''offset'' || — || — ||align=left| JP β''disp5'' || 3 ||align=left| PC β PC β 32 + ''offset''; jump 1–32 bytes backward |- ! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || Cycles || Description |} {{notelist|refs= {{efn|name=feature|Only on "feature family" (COP888/COP8SA) cores; not present on "basic family" (COP800) cores.}} {{efn|name=flash|Only on "flash family" (COP8TA/COP8C) models with boot ROM for [[in-system programming]].}} {{efn|name=dir|Operand may be changed from {{code|[B]}} to 8-bit absolute address with a [[#DIR|{{code|DIR}} prefix]] (+2 bytes, +3 cycles).}} }}
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