Editing Celeron (section)

=== P6-based Celerons ===
{{Main|List of Intel Celeron microprocessors#P6 based Celerons}}

==== {{Anchor|Covington}}Covington ====
[[Image:KL Intel Celeron Covington.jpg|right|thumb|180px|Intel Celeron Covington]]
Launched in April 1998, the first ''Covington'' Celeron was essentially a 266&nbsp;MHz Pentium II manufactured without any secondary cache at all.<ref>{{cite magazine |last=Slater |first=Michael |title=Microprocessors have PCs humming |url=http://www.eetimes.com/myf98/ao_slater.html |magazine=[[EE Times]] |date=May 27, 1998 |access-date=July 30, 2007}}</ref> Covington also shared the 80523 product code of Deschutes. Although clocked at 266 or 300&nbsp;MHz (frequencies 33 or 66&nbsp;MHz higher than the desktop version of the Pentium w/MMX), the cacheless Celerons had trouble outcompeting the parts they were designed to replace.<ref name="S7toS1" /> Substantial numbers were sold on first release, largely on the strength of the Intel name, but the Celeron quickly achieved a poor reputation both in the trade press and among computer professionals.<ref>{{cite web |last=Zisman |first=Alex |title=Say No to Celeron |url=http://www.zisman.ca/Articles/1998/Celeron.html |work=Canadian Computer Wholesaler |date=June 1998 |access-date=July 30, 2007}}</ref> The initial market interest faded rapidly in the face of its poor performance, and with sales at a very low level, Intel felt obliged to develop a substantially faster replacement as soon as possible. Nevertheless, the first Celerons were quite popular among some overclockers, for their flexible [[overclocking|overclockability]] and reasonable price.<ref name="S7toS1" /> Covington was only manufactured in [[Slot 1]] SEPP format.

==== {{Anchor|Mendocino}}Mendocino ====
{{redirect|Mendocino (microprocessor)|the AMD mobile APU|List of AMD mobile processors#Mendocino (7020 series, Zen2/RDNA2 based)}}
[[Image:Intel Celeron 300A MHz.jpg|thumb|180px|right|Intel Celeron Mendocino 300&nbsp;MHz in SEPP package]]
[[Image:KL Intel Celeron Mendocino Top.jpg|thumb|150px|right|Top of a Mendocino-core Socket 370 Celeron (PPGA package)]] [[Image:KL Intel Celeron Mendocino S370.jpg|thumb|150px|right|Underside of a Mendocino-core Socket 370 Celeron, 333&nbsp;MHz]]
[[File:Intel Celeron 500MHz Mendocino SL3LQ (PNG).png|thumb|Intel Celeron 500MHz Mendocino die shot]]
The ''Mendocino'' Celeron, launched August 24, 1998, was the first retail CPU to use on-die [[L2 cache]]. Whereas Covington had no secondary cache at all, Mendocino included 128&nbsp;KB of L2 cache running at full clock rate. The first Mendocino-core Celeron was clocked at a then-modest 300&nbsp;MHz but offered almost twice the performance of the old cacheless Covington Celeron at the same clock rate. To distinguish it from the older Covington 300&nbsp;MHz, Intel called the Mendocino core Celeron ''300A''.<ref name="BigCPUShootout">{{cite news|last=Pabst|first=Thomas|title=Big CPU Shoot Out: Intel Launches New Celeron with Mendocino Core and Pentium II 450|url=http://www.tomshardware.com/1998/08/24/big_cpu_shoot_out/|archive-url=https://archive.today/20130204153422/http://www.tomshardware.com/1998/08/24/big_cpu_shoot_out/|url-status=dead|archive-date=February 4, 2013|publisher=[[Tom's Hardware Guide]]|date=August 24, 1998|access-date=July 30, 2007}}</ref> Although the other Mendocino Celerons (the 333&nbsp;MHz part, for example) did not have an ''A'' appended, some people call all Mendocino processors ''Celeron-A'' regardless of clock rate.

The new Mendocino-core Celeron was a good performer from the outset. Indeed, most industry analysts regarded the first Mendocino-based Celerons as ''too'' successful—performance was sufficiently high to not only compete strongly with rival parts, but also to attract buyers away from Intel's high-profit flagship, the Pentium II. [[Overclocking|Overclockers]] soon discovered that, given a high-end [[motherboard]], many Celeron 300A CPUs could run reliably at 450&nbsp;MHz. This was achieved by simply increasing the [[front-side bus]] (FSB) clock rate from the stock 66&nbsp;MHz to the 100&nbsp;MHz clock of the [[Pentium II]], helped by several facts: the 440BX chipset with nominal support for 100&nbsp;MHz and correspondent memory had already been on the market, and the internal L2 cache was more tolerant to overclocking than external cache chips, which already had to run at half-CPU speed by design. At this frequency, the budget Mendocino Celeron rivaled the fastest x86 processors available.<ref name="BigCPUShootout" /> Some motherboards were designed to prevent this modification, by restricting the Celeron's front side bus to 66&nbsp;MHz. However, [[overclocking|overclockers]] soon found that putting tape over pin B21 of the Celeron's interface slot circumvented this, allowing a 100&nbsp;MHz bus.<ref>{{cite web|url=http://www.tomshardware.com/reviews/66-mhz-slot-1-cpus-running-100-mhz,66.html|title=How to Get All 66 MHz Slot 1 CPUs Running 100 MHz|author=Thomas Pabst|work=Tom's Hardware|date=May 14, 1998 }}</ref>

At the time on-die cache was difficult to manufacture; especially [[L2 cache|L2]] as more of it is needed to attain an adequate level of performance. A benefit of on-die cache is that it operates at the same clock rate as the CPU. All other Intel CPUs at that time used motherboard mounted or slot mounted secondary [[L2 cache]], which was very easy to manufacture, cheap, and simple to enlarge to any desired size (typical cache sizes were 512&nbsp;KB or 1&nbsp;MB), but they carried the performance penalty of slower cache performance, typically running at a [[Front-side bus|FSB]] frequency of 60 to 100&nbsp;MHz. The Pentium II's 512&nbsp;KB of L2 cache was implemented with a pair of relatively high-performance L2 cache chips mounted on a special-purpose board alongside the processor itself, running at half the processor's clock rate and communicating with the CPU through a special [[back-side bus]]. This method of cache placement was expensive and imposed practical cache-size limits, but allowed the Pentium II to be clocked higher and avoided front side bus RAM/L2 cache contention typical with motherboard-placed L2 cache configurations.<ref>{{cite news|last=Joch |first=Alan |title=Buses: Front-side and backside |url=http://www.itworld.com/Comp/1091/CWD010430STO60015/ |publisher=ITworld.com |date=April 30, 2001 |access-date=July 30, 2007 |url-status=dead |archive-url=https://web.archive.org/web/20010502134148/http://www.itworld.com/Comp/1091/CWD010430STO60015/ |archive-date=May 2, 2001 |df=dmy }}</ref>

Over time, newer Mendocino processors were released at 333, 366, 400, 433, 466, 500, and 533&nbsp;MHz. The Mendocino Celeron CPU came only designed for a 66&nbsp;MHz front-side bus, but this would not be a serious performance bottleneck until clock rates reached higher levels.

The Mendocino Celerons also introduced new packaging. When the Mendocinos debuted they came in both a Slot 1 SEPP and [[Socket 370]] [[Pin grid array#Plastic|PPGA]] package. The Slot 1 form had been designed to accommodate the off-chip cache of the Pentium II and had mounting problems with motherboards. Because all Celerons are a single-chip design, however, there was no reason to retain the slot packaging for L2 cache storage, and Intel discontinued the Slot 1 variant; beginning with the 466&nbsp;MHz part, only the PPGA Socket 370 form was offered. (Third-party manufacturers made motherboard slot-to-socket adapters (nicknamed [[Slotket]]s) available for a few dollars, which allowed, for example, a Celeron 500 to be fitted to a Slot 1 motherboard.) One interesting note about the PPGA Socket 370 Mendocinos is they supported [[symmetric multiprocessing]] (SMP), and there was at least one motherboard released (the [[ABIT BP6]]) which took advantage of this fact.

The Mendocino also came in a mobile variant, with clock rates of 266, 300, 333, 366, 400, 433 and 466&nbsp;MHz.

In Intel's "Family/Model/Stepping" scheme, Mendocino CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the related ''Dixon'' Mobile Pentium II variant.

==== Coppermine-128 ====
 {{multiple image
 | total_width = 320
 | image1      = Celeron Coppermine-128 600.jpg
 | caption1    = Celeron ''Coppermine 128'' 600&nbsp;MHz ([[FC-PGA]] package)
 | image2      = Celeron Coppermine-128 600 back.jpg
 | caption2    = Underside of a Celeron ''Coppermine 128'', 600&nbsp;MHz
 }}
The next generation Celeron was the '' '[[Coppermine (microprocessor)|Coppermine]]-128' '' (sometimes known as the ''Celeron II''). These were a derivative of Intel's ''Coppermine'' [[Pentium III]] and were released on March 29, 2000.<ref>{{cite news |last=Hachman |first=Mark |title=Intel launches Celerons with SIMD instruction-set extensions |url=http://www.my-esm.com/digest/story/OEG20000329S0006 |publisher=My-ESM |date=March 29, 2000 |access-date=July 31, 2007 |archive-url=https://web.archive.org/web/20070927070052/http://www.my-esm.com/digest/story/OEG20000329S0006 |archive-date=September 27, 2007 |url-status=dead |df=dmy }}</ref> This Celeron used a Coppermine core with half of its L2 cache switched off, resulting in 128&nbsp;KB of 4-way associative on-chip L2 cache as on the Mendocino, and was initially likewise restricted to a 66&nbsp;MHz Front Side Bus speed. Despite the halved associativity on the L2 cache, which reduced hit rates compared to the full Coppermine design, it kept the 256-bit wide L2 cache bus, which meant an advantage compared to Mendocino and older Katmai/Pentium II designs, which all had a 64-bit datapath to their L2 caches.<ref>{{cite web|url=https://www.anandtech.com/show/519/5|title=Intel Celeron 600 "Coppermine128"|first=Anand Lal|last=Shimpi|website=anandtech.com|access-date=April 4, 2018}}</ref><ref>{{cite web|url=https://www.anandtech.com/show/568/2|title=Intel Celeron 700|first=Anand Lal|last=Shimpi|website=anandtech.com|access-date=April 4, 2018}}</ref> [[Streaming SIMD Extensions|SSE]] instructions were also enabled.

All Coppermine-128s were produced in the same [[FCPGA]] Socket 370 format that most Coppermine Pentium III CPUs used. These Celeron processors began at 533&nbsp;MHz and continued through 566, 600, 633, 667, 700, 733, and 766&nbsp;MHz. Because of the limitations of the 66&nbsp;MHz bus, there were diminishing returns on performance as clock rates increased. On January 3, 2001, Intel switched to a 100&nbsp;MHz bus with the launch of the 800&nbsp;MHz Celeron, resulting in a significant performance-per-clock improvement.<ref>{{cite news|last=Lal Shimpi| first=Anand| author-link=Anand Lal Shimpi | title=Intel Celeron 800: The first 100&nbsp;MHz FSB Celeron | url=http://www.anandtech.com/showdoc.aspx?i=1393&p=1 | publisher=[[AnandTech]]|date=January 3, 2001|access-date=July 30, 2007}}</ref> All Coppermine-128 CPUs from 800&nbsp;MHz and higher use the 100&nbsp;MHz front side bus. Various models were made at 800, 850, 900, 950, 1000, and 1100&nbsp;MHz.

In Intel's "Family/Model/Stepping" scheme, Coppermine Celerons and Pentium IIIs are family 6, model 8 and their Intel product code is 80526.

==== Tualatin-256 ====
[[Image:Tualeron 1200.jpg|thumb|150px|A Tualatin-core Celeron 1.2&nbsp;GHz (''Tualeron'') (FC-PGA2 package)]]
These Celeron processors, released initially at 1.2&nbsp;GHz on October 2, 2001,<ref>{{cite news|last=Sigvartsen |first=Ana |title=Intel's Celeron reaches 1.2&nbsp;GHz |url=http://www.infosatellite.com/news/2001/10/j031001celeron_12ghz.html |publisher=Infosatellite.com |date=October 2, 2001 |access-date=July 31, 2007 |url-status=dead |archive-url=https://web.archive.org/web/20071012160212/http://infosatellite.com/news/2001/10/j031001celeron_12ghz.html |archive-date=October 12, 2007 }}</ref> were based on the Pentium III ''' '[[Pentium III#Tualatin|Tualatin]]'''' core and made with a 0.13 micrometer process for the [[FCPGA|FCPGA 2]] Socket 370. They were nicknamed "Tualeron" by some enthusiasts — a portmanteau of the words [[Pentium III#Tualatin|Tualatin]] and Celeron. Some software and users refer to the chips as ''Celeron-S'', referring to the chip's lineage with the Pentium III-S, but this is not an official designation. Intel later released 1&nbsp;GHz and 1.1&nbsp;GHz parts (which were given the extension ''A'' to their name to differentiate them from the Coppermine-128 of the same clock rate they replaced).<ref>{{cite news|last=Sigvartsen|first=Ana|title=Intel's Celeron gets major power boost|url=http://www.infosatellite.com/news/2001/12/h071201celeron_tualatin.html|publisher=Infosatellite.com|date=December 7, 2001|access-date=July 31, 2007|url-status=dead|archive-url=https://web.archive.org/web/20071012160217/http://infosatellite.com/news/2001/12/h071201celeron_tualatin.html|archive-date=October 12, 2007|df=dmy-all}}</ref> A 1.3&nbsp;GHz chip, launched January 4, 2002,<ref>{{cite news|last=Sigvartsen|first=Ana|title=Intel launches Celeron 1.3&nbsp;GHz|url=http://www.infosatellite.com/news/2002/01/h040102intel_celeron_3ghz.html|publisher=Infosatellite.com|date=January 4, 2002|access-date=July 31, 2007|url-status=dead|archive-url=https://web.archive.org/web/20071012160232/http://infosatellite.com/news/2002/01/h040102intel_celeron_3ghz.html|archive-date=October 12, 2007|df=dmy-all}}</ref> and finally a 1.4&nbsp;GHz chip, launched May 15, 2002 (the same day as the 1.7&nbsp;GHz Willamette-based Celeron launch),<ref>{{cite news|last=Sigvartsen|first=Ana|title=Intel launches Celeron with new core|url=http://www.infosatellite.com/news/2002/05/a160502celerons.html|publisher=Infosatellite.com|date=May 16, 2002|access-date=July 31, 2007|url-status=dead|archive-url=https://web.archive.org/web/20071012160237/http://infosatellite.com/news/2002/05/a160502celerons.html|archive-date=October 12, 2007|df=dmy-all}}</ref> marked the end of the Tualatin-256 line.

The most significant differences compared to the Pentium III Tualatin are a lower 100&nbsp;MHz bus and fixed 256&nbsp;KB of L2 cache (whereas the Pentium III was offered with either 256&nbsp;KB or 512&nbsp;KB L2 cache); cache associativity stayed at 8-way,<ref>download.intel.com/support/processors/celeron/sb/29859604.pdf</ref> although the newly introduced data prefetching appears to have been disabled.<ref>{{cite web|url=https://www.realworldtech.com/data-prefetching/|title=Data Prefetch Logic - What is it Worth?|website=www.realworldtech.com|access-date=April 4, 2018}}</ref> Furthermore, the Tualatin-256's L2 cache has a higher latency which boosted manufacturing yields for this budget CPU.{{Citation needed|date=December 2017}} On the other hand, this improved stability when overclocking and most of them had no problem working at 133&nbsp;MHz FSB for a substantial performance increase.

Despite offering much improved performance over the Coppermine Celeron it superseded, the Tualatin Celeron still suffered stiff competition from AMD's [[Duron]] budget processor.<ref>{{cite news|first=Frank| last=Völkel |author2=Töpelt, Bert|title=Intel vs. AMD: Celeron 1300 vs. Duron 1200|url=http://www.tomshardware.com/2002/01/03/intel_vs/|publisher=[[Tom's Hardware Guide]] | date=January 3, 2002|access-date=July 31, 2007}}</ref> Intel later responded by releasing the NetBurst Willamette Celeron, and for some time Tualatin Celerons were manufactured and sold in parallel with the Pentium 4-based Celerons that replaced them.

In Intel's "Family/Model/Stepping" scheme, Tualatin Celerons and Pentium IIIs are family 6, model 11 and their Intel product code is 80530.