Editing DDR2 SDRAM (section)

=== Overview ===
[[File:Samsung-1GB-DDR2-Laptop-RAM.jpg|thumb|PC2-5300 DDR2 SO-DIMM (for notebooks)]]
[[Image:Desktop_DDR_Memory_Comparison.svg|thumb|right|Comparison of memory modules for desktop PCs (DIMM)]]
[[Image:Laptop_SODIMM_DDR_Memory_Comparison_V2.svg|thumb|right|Comparison of memory modules for portable/mobile PCs (SO-DIMM)]]

The key difference between DDR2 and DDR SDRAM is the increase in prefetch length. In DDR SDRAM, the prefetch length is two bits for every bit in a word; whereas it is four bits in DDR2 SDRAM. During an access, four bits are read or written to or from a four-bit-deep prefetch queue. This queue receives or transmitts its data over the data bus in two data bus clock cycles (each clock cycle transferrs two bits of data). Increasing the prefetch length allowed DDR2 SDRAM to double the rate at which data can be transferred over the data bus without a corresponding doubling in the rate at which the DRAM array can be accessed. DDR2 SDRAM is designed with such a scheme to avoid an excessive increase in power consumption.

DDR2's bus frequency is boosted by electrical interface improvements, [[on-die termination]], [[prefetch buffer]]s and off-chip drivers. However, [[memory latency|latency]] is greatly increased as a trade-off. The DDR2 prefetch buffer is four&nbsp;bits deep, whereas it is two&nbsp;bits deep for DDR. While DDR SDRAM has typical read latencies of between two and three bus cycles, DDR2 may have read latencies between three and nine cycles, although the typical range is between four and six. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency.

Another cost of the increased bandwidth is the requirement that the chips are packaged in a more expensive and difficult to assemble [[Ball grid array|BGA]] package as compared to the [[TSSOP]] package of the previous memory generations such as [[DDR SDRAM]] and [[SDR SDRAM]].  This packaging change was necessary to maintain signal integrity at higher bus speeds.

Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage (1.8&nbsp;V compared to DDR's 2.5&nbsp;V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest available data rates.

According to JEDEC<ref>[http://www.jedec.org/download/search/JESD208.pdf JEDEC JESD 208] (section 5, tables 15 and 16)</ref> the maximum recommended voltage is 1.9 volts and should be considered the absolute maximum when memory stability is an issue (such as in servers or other mission critical devices). In addition, JEDEC states that memory modules must withstand up to 2.3 volts before incurring permanent damage (although they may not actually function correctly at that level).