Editing DEC PRISM (section)

===RISC===
During the 1970s, [[IBM]] had been carrying out studies of the performance of their computer systems and found, to their surprise, that 80% of the computer's time was spent performing only five operations. The hundreds of other instructions in their ISAs, implemented using microcode, went almost entirely unused. The presence of the microcode introduced a delay when the instructions were decoded, so even when one called one of those five instructions directly, it ran slower than it could if there was no microcode. This led to the [[IBM 801]] design, the first modern [[RISC]] processor.<ref>{{Cite journal | last1 = Cocke | first1 = John | last2 = Markstein | first2 = Victoria | doi = 10.1147/rd.341.0004 | url = https://www.cis.upenn.edu/~milom/cis501-Fall11/papers/cocke-RISC.pdf | title = The evolution of RISC technology at IBM | journal = IBM Journal of Research and Development | volume = 34 | issue = 1 | pages = 4–11 | date = January 1990 | access-date = 2022-10-05}}</ref>

Around the same time, in 1979, [[David Patterson (computer scientist)|Dave Patterson]] was sent on a [[sabbatical]] from [[University of California, Berkeley]] to help DEC's west-coast team improve the VAX microcode. Patterson was struck by the complexity of the coding process and concluded it was untenable. He first wrote a paper on ways to improve microcoding, but later changed his mind and decided microcode itself was the problem. He soon started the [[Berkeley RISC]] project.<ref>{{cite web |website=AM SIGARCH |date=30 May 2018 |first=David |last=Patterson |title=RISCy History |url=https://www.sigarch.org/riscy-history/}}</ref> The emergence of RISC sparked off a long-running debate within the computer industry about its merits; when Patterson first outlined his arguments for the concept in 1980, a dismissive dissenting opinion was published by DEC.<ref>{{cite web |url= http://www-inst.cs.berkeley.edu/~n252/paper/RISC-clark.pdf |archive-url=https://web.archive.org/web/20190418165128/http://www-inst.cs.berkeley.edu/~n252/paper/RISC-clark.pdf |archive-date=18 April 2019 |title=Comments on "The Case for the Reduced Instruction Set Computer," by Patterson and Ditzel |first1=Douglas  |last1=Clark |first2=William |last2=Streck |date=September 1980}}</ref>

By the mid-1980s practically every company with a processor design arm began exploring the RISC approach. In spite of any official disinterest, DEC was no exception. In the period from 1982 to 1985, no fewer than four attempts were made to create a RISC chip at different DEC divisions. '''Titan''' from DEC's Western Research Laboratory (WRL) in [[Palo Alto, California]] was a high-performance [[Emitter-coupled logic|ECL]] based design that started in 1982, intended to run [[Unix]]. '''SAFE''' (''Streamlined Architecture for Fast Execution'') was a [[64-bit]] design that started the same year, designed by [[Alan Kotok]] (of [[Spacewar!]] fame) and Dave Orbits and intended to run VMS. '''HR-32''' (''Hudson, RISC, 32-bit'') started in 1984 by Rich Witek and [[Dan Dobberpuhl]] at the [[Hudson, MA]] fab, intended to be used as a [[Coprocessor|co-processor]] in [[VAX]] machine. The same year [[Dave Cutler]] started the '''CASCADE''' project at DECwest in Bellevue, Washington.{{sfn|Supnik|2008}}