Editing Datapoint 2200 (section)

== Instruction set ==
Instructions are one to three bytes long, consisting of an initial opcode byte, followed by up to two bytes of operands which can be an immediate operand or a program address. Instructions operate on 8-bits only; there are no 16-bit operations. There is only one mechanism to address data memory: indirect addressing pointed to by a concatenation of the H and L registers, referenced as M. The 2200 does, however, support 13-bit program addresses. It has automatic CALL and RETURN instructions for multi-level subroutine calls and returns which can be conditionally executed, like jumps. Direct copying may be made between any two registers or a register and memory. Eight math/logic functions are supported between the accumulator (A) and any register, memory, or an immediate value. Results are always deposited in A. Most instructions are executed in 16 μs, 24 μs, or a leisurely 520 μs when accessing M. The 520 μs represents the delay of the 2200's shift register memory to fully recirculate back to the next instruction. Branch type instructions take a variable amount of time (24 μs to 520 μs) depending on the distance of the branch.
{|class="wikitable" style="text-align:center"
|+Datapoint 2200 version I instruction set
!colspan=8| Opcode ||colspan=2| Operands ||rowspan=2| Mnemonic || rowspan=2| Time μs ||rowspan=2| Description
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || X || &mdash; || &mdash; ||align=left| HALT || &mdash; ||align=left| Halt
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| SLC || 16 ||align=left| A<sub>1-7</sub> ← A<sub>0-6</sub>; A<sub>0</sub> ← Cy ← A<sub>7</sub>
|-
| 0 || 0 ||colspan=3|CC || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| Rcc (RETURN conditional) || 16/† ||align=left| If cc true, P ← (stack)
|-
| 0 || 0 ||colspan=3|ALU || 1 || 0 || 0 || ''data'' || &mdash; ||align=left| AD AC SU SB ND XR OR CP ''data'' || 16 ||align=left| A ← A [ALU operation] data
|-
| 0 || 0 ||colspan=3|DDD || 1 || 1 || 0 || ''data'' || &mdash; ||align=left| Lr ''data'' (Load r with immediate data) || 16 ||align=left| DDD ← data (except M)
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| RETURN || † ||align=left| P ← (stack)
|-
| 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| SRC || 16 ||align=left| A<sub>0-6</sub> ← A<sub>1-7</sub>; A<sub>7</sub> ← Cy ← A<sub>0</sub>
|-
| 0 || 1 ||colspan=3|CC || 0 || 0 || 0 || ''addlo'' || ''addhi'' ||align=left| Jcc ''add'' (JMP conditional) || 24/† ||align=left| If cc true, P ← add
|-
| 0 || 1 || 0 || 0 || 0 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| INPUT || 16 ||align=left| A ← input
|-
| 0 || 1 ||colspan=5|command || 1 || &mdash; || &mdash; ||align=left| EX ''command'' (external command)|| 16 ||align=left| command ← A (coded 8-31 only)
|-
| 0 || 1 ||colspan=3|CC || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| Ccc ''add'' (CALL conditional) || 24/† ||align=left| If cc true, (stack) ← P, P ← add
|-
| 0 || 1 || 0 || 0 || 0 || 1 || 0 || 0 || ''addlo'' || ''addhi'' ||align=left| JMP ''add'' || † ||align=left| P ← add
|-
| 0 || 1 || 0 || 0 || 0 || 1 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| CALL ''add'' || † ||align=left| (stack) ← P, P ← add
|-
| 1 || 0 ||colspan=3|ALU ||colspan=3|SSS || &mdash; || &mdash; ||align=left| ADr ACr SUr SBr NDr XRr ORr CPr || 16/520 ||align=left| A ← A [ALU operation] SSS
|-
| 1 || 1 || 0 || 0 || 0 || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| NOP || 16 ||align=left| No operation (Actually LAA)
|-
| 1 || 1 ||colspan=3|DDD ||colspan=3|SSS || &mdash; || &mdash; ||align=left| Lds (Load d with s) ||16/520 ||align=left| DDD ← SSS
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| HALT || &mdash; ||align=left| Halt
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || Time μs  || Description
|-
!colspan=13|
|-
!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU
|-
|colspan=5| A || 0 || 0 || 0 ||colspan=2|FC, C false ||align=left|ADr AD (A ← A + arg)||colspan=2|† Variable. Can be from 24 μs to 520 μs.
|-
|colspan=5| B || 0 || 0 || 1||colspan=2|FZ, Z false||align=left|ACr AC (A ← A + arg + Cy)
|-
|colspan=5| C || 0 || 1 || 0||colspan=2|FS, S false ||align=left|SUr SU (A ← A - arg)
|-
|colspan=5| D || 0 || 1 || 1||colspan=2|FP, P odd ||align=left|SBr SB (A ← A - arg - Cy)
|-
|colspan=5| E || 1 || 0 || 0||colspan=2|TC, C true ||align=left|NDr ND (A ← A ∧ arg)
|-
|colspan=5| H || 1 || 0 || 1||colspan=2|TZ, Z true ||align=left|XRr XR (A ← A ⊻ arg)
|-
|colspan=5| L || 1 || 1 || 0||colspan=2|TS, S true ||align=left|ORr OR (A ← A ∨ arg)
|-
|colspan=5| M || 1 || 1 || 1||colspan=2|TP, P even ||align=left|CPr CP (A - arg)
|-
!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU
|}

===Performance===
Although the Datapoint 2200 version I is somewhat faster than an [[Intel 8008]] on register instructions, any reference to the 2200's shift-register memory incurs a large 520 μs delay. Also any JMP, CALL, or RETURN can incur a variable delay up to 520 μs depending on the distance to the new address. The parallel-architecture Datapoint 2200 version II is much faster than either.<ref name="2200ref"/><ref name="8008man">{{cite book |title=8008 8 Bit Parallel Central Processor Unit |date=November 1973 |publisher=Intel |pages=14, 17 |edition=Rev 4, Second Printing |url=http://www.bitsavers.org/components/intel/MCS8/Intel_8008_8-Bit_Parallel_Central_Processing_Unit_Rev4_Nov73.pdf |access-date=30 April 2024}}</ref>

{|class="wikitable" style="text-align:center"
|-
!colspan=5|Instruction|| Description || Datapoint 2200 ver I μs|| 500&nbsp;kHz Intel 8008 μs|| Datapoint 2200 ver II μs
|-
|colspan=5|ADB|| Add B to A || 16 || 20 || 3.2
|-
|colspan=5|ADI nn|| Add nn immediate to A || 16 || 32 || 4.8
|-
|colspan=5|ADM|| Add memory to A || 520 || 32 || 4.8
|-
|colspan=5|JMP nnnn|| Jump to nnnn || 24-520 || 44 || 6.4
|-
|colspan=5|CALL+RET|| Call and Ret combined|| 520 || 64 || 9.6
|-
|colspan=5|Rcc (false)|| Conditional return not taken || 16 || 12 || 3.2
|}

===Code example===
The following Datapoint 2200 assembly source code is for a subroutine named MEMCPY that copies a block of data bytes from one location to another. Because the byte counter is only 8 bits, there is enough room to load all the subroutine parameters into the 2200's register file. Datapoint 2200 version I transfers 374 bytes per second using this routine. A 500&nbsp;kHz Intel 8008 executes this code almost four times faster, transferring 1,479 bytes per second. Datapoint 2200 version II is much faster than either at 9,615 bytes per second.<ref name="2200ref">{{cite book |title=Datapoint 2200 Reference |date=1972 |publisher=Computer Terminal Corporation |url=http://www.bitsavers.org/pdf/datapoint/2200/2200_Reference_Manual.pdf |access-date=16 September 2024}}</ref><ref name="8008man" /> If more than an 8-bit count is needed, a more complicated copy routine with parameters held in memory would be required.
<!--This routine was assembled by brain and might contain errors-->
{|
|
<pre>
                   
                   
                   
                   
                   
                   
                   
                   
    
002000  317    
002001  206 020 004
002004  371        
002005  206 020 004
002010  302
002011  024 001
002013  320
002014  110 000 004
002017  007        
        
          
002020  306
002021  364        
002022  004 001
002024  340
002025  305        
002026  353
002027  014 000
002031  330
002032  007        
002032             
</pre>
|
<syntaxhighlight lang="nasm">
; MEMCPY --
; Copy a block of memory from one location to another
;
; Entry parameters in registers
;       HL: 13-bit address of source data block
;       DE: 13-bit address of target data block
;       C: 8-bit count of bytes to copy. (1 to 256 bytes)
 
            ORG     2000Q       ;Code at 002000 octal
MEMCPY      LBM                 ;Read source byte into B
            CALL    XCHGI       ;Exchange HL<->DE and increment DE
            LMB                 ;Save B to target byte
            CALL    XCHGI       ;Exchange HL<->DE and increment DE
            LAC                 ;Decrement byte counter in C
            SU      1
            LCA
            JFZ     MEMCPY     ;Continue for all bytes
            RETURN
            
;Exchange DE and HL register pairs then increment DE as 16 bits
XCHGI       LAL                 ;Exchange L and E
            LLE
            AD      1           ;and inc E, low byte of DE
            LEA
            LAH                 ;Exchange H and D
            LHD
            AC      0           ;proagate Cy into D
            LDA
            RETURN
            END
</syntaxhighlight>
|}