Editing Fault model (section)

==Fault collapsing==
There are two main ways for collapsing fault sets into smaller sets.

===Equivalence collapsing===
It is possible that two or more faults produce same faulty behavior for all input patterns. These faults are called equivalent faults. Any single fault from the set of equivalent faults can represent the whole set. In this case, much less than k×n fault tests are required for a circuit with n signal line. removing equivalent faults from entire set of faults is called fault collapsing. fault collapsing significantly decreases the number of faults to check.


In the example diagram, red faults are equivalent to the faults that being pointed to with the arrows, so those red faults can be removed from the circuit. In this case, the fault collapse ratio is 12/20.

===Dominance collapsing===
[[File:Fault dominance example.png|thumbnail|right|Fault dominance example for a NAND gate]]
Fault F is called dominant to F' if all tests of F' detects F. In this case, F can be removed from the fault list. If F dominates F' and F' dominates F, then these two faults are equivalent.<ref>[http://web.eecs.umich.edu/~mazum/F02/lectures/lecmazum3.pdf "Fault Modeling"],''[University of Michigan]''</ref>

In the example, a NAND gate has been shown, the set of all input values that can test output's SA0 is {00,01,10}. the set of all input values that can check first input's SA1 is {01}. In this case, output SA0 fault is dominant and can be removed from fault list.

===Functional collapsing===
Two faults are functionally equivalent if they produce identical faulty functions<ref>[http://www.eng.auburn.edu/~vagrawal/TALKS/VDAT07_Rev7.ppt "Using Hierarchy in Design Automation:The Fault Collapsing Problem "],[''11th VLSI Design and Test Symposium Kolkata, August 8–11, 2007'']</ref> or we can say, two faults are functionally equivalent if we can not distinguish them at primary outputs (PO) with any input test vector.<ref>Andreas Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi, [http://www.eecg.utoronto.ca/~veneris/jetta4.pdf "Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG"]</ref>