Editing IBM ROMP (section)

==Implementation==
The ROMP is a [[scalar processor]] with a three-stage pipeline.<ref name="Furber"/> In the first stage, if there are instructions in the 16-byte instruction prefetch buffer, an instruction was fetched, decoded, and operands from the general-purpose register file read. The instruction prefetch buffer read a 32-bit word from the memory whenever the ROMP was not accessing it.<ref name="Furber"/> Instructions were executed in the second stage, and written back into the general-purpose register file in the third stage. The ROMP used a bypass network and appropriately scheduled the register file reads and writes to support back-to-back execution of dependent instructions.<ref name="Furber"/> Most register-to-register instructions were executed in one cycle; of the 118 instructions, 84 had a single-cycle latency.<ref name="Seymour_1986-06-10">{{cite magazine |last=Seymour |first=Jim |date=10 June 1986 |title=RISC Architecture |magazine=[[PC Magazine]] |page=113}}</ref> The ROMP had an IBM-developed companion [[integrated circuit]] which was code-named Rosetta during development.<ref>{{cite magazine |last=Chandler |first=David |title=The ROMP Is Not Just A Lark |magazine=UNIX Review |date=1986}}</ref> Rosetta was a [[memory management unit]] (MMU), and it provided the ROMP with address translation facilities, a [[translation lookaside buffer]], and a store buffer.<ref name="Furber"/>

The ROMP and Rosetta were originally implemented in an IBM 2{{nbsp}}μm [[silicon-gate]] [[n-channel|NMOS technology]] with two levels of metal interconnect.<ref name="IBM_book">{{cite book |editor-first=Frank |editor-last=Waters |title=The IBM RT Personal Computer Technology |page=8}}</ref><ref name="Bambrick">{{cite magazine |last=Bambrick |first=Richard |date=27 January 1986 |title=IBM's New RISC Processor Based on 10-Year Project |magazine=[[Electronic News]]}}</ref> The ROMP consists of 45,000 transistors and is 7.65{{nbsp}}×{{nbsp}}7.65{{nbsp}}mm large (58.52{{nbsp}}mm<sup>2</sup>), while Rosetta consists of 61,500 transistors and is 9.02{{nbsp}}×{{nbsp}}9.02{{nbsp}}mm large (81.36{{nbsp}}mm<sup>2</sup>). Both are packaged in 135-pin [[ceramic pin grid array]]s.<ref name="Bambrick" /> A CMOS version of the ROMP and Rosetta (called ROMP-C and Rosetta-C) was later developed.