Editing Intel i960 (section)

==i960 variants==

===80960MC===
The i960MC included all of the features of the original BiiN system; but these were simply not mentioned in the specifications, leading some{{who|date=July 2018}} to wonder why the i960MC was so large and had so many pins - 53 out of 132<ref>{{Cite web |url=http://www.bitsavers.org/components/intel/i960/271080-006_80960MC_Advance_Information_Jan91.pdf |title=80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT |date=1990 |access-date=2023-04-05 |website=Intel |pages=24–29}}</ref> - labeled "no connect". Later iterations of the i960, like the 80960Jx series, have a more typical number of "do no connect" and use more power and ground pins and have additional I/O pins instead.<ref>{{Cite web |url=http://www.bitsavers.org/components/intel/i960/80960JA_Data_Sheet_Mar98.pdf |title=80960JA/JF/JD/JT 3.3 V EMBEDDED 32-BIT MICROPROCESSOR |date=March 1998 |access-date=2023-04-05 |website=Intel |pages=22–25}}</ref> However, these "no connect" pins are actually not connected internally and unrelated to the BiiN feature set - the silicon die inside does not have bond pads for them.<ref>{{Cite web |url=http://www.righto.com/2023/07/the-complex-history-of-intel-i960-risc.html |title=The complex history of the Intel i960 RISC processor |date=2023-07-01 |access-date=2023-07-01 |website= |last=Shirriff |first=Ken |quote=The original i960 chips (KA/KB/MC/XA) have a large number of pins that are not connected (marked NC on the datasheet) [...] checking the datasheets shows that all four chips have the same pinout; there are no pins connected only in the more advanced versions. Second, looking at the packaged chip (below) explains why so many pins are unconnected: much of the chip has no bond pads, so there is nothing to connect the pins to.}}</ref>

The 80960MC contains an on-chip [[memory management unit]] and supports [[Fault tolerance|fault tolerant systems]] in conjunction with Intel's M82965 Bus Extension Unit as well. Both chips meets [[MIL-STD-883|MIL-STD-883C]] standard. Both chips became available in the first quarter of 1989 with the price of US$2400 and US$1700 respectively. Extended temperature samples became available in August 1988 as well.<ref name="Lewnes, Ann 1988, page 2">Lewnes, Ann, "Intel's 80960 & 80376 Standouts in the 32-Bit Crowd", Intel Corporation, Microcomputer Solutions, July/August 1988, page 2</ref>

It contains 32 32-bit registers, a 512 byte instruction cache, a [[Call stack#Structure|stack frame cache]], a high speed 32-bit [[Direct memory access|multiplexed burst bus]], and an interrupt controller.<ref name="Ormsby, Jon 1988, page 9">Ormsby, Jon, Editor, "New Product Focus: Components: Intel Enters The World Of 32-Bit Embedded Control", Intel Corporation, Microcomputer Solutions, May/June 1988, page 9</ref> It also has 256 interrupt vectors and 32 levels of interrupt priority.<ref name="Lewnes, Ann 1988, page 2"/>

===80960XA===
The 80960XA is a military member of the i960 family, implementing the Extended architecture, a superset of the military 80960MC. It supports object-oriented programming with a 33rd tag bit in hardware, a [[Capability-based security|Capability]]. It supports the Joint Industrial Avionics Working Group (JIAWG) 32-bit ISA standard.<ref name="80960xa" />

===80960KA, 80960KB===
A version of the RISC core without memory management or an [[floating point unit|FPU]] became the i960KA, and the RISC core with an FPU became the i960KB. The versions were, however, identical internally—only the labeling was different. This meant the CPUs were much larger than necessary for the "actually supported" feature sets, and as a result, more expensive to manufacture than they needed to be.

These processors contain more than 350,000 transistors. These processors can perform around 7.5 [[VAX Unit of Performance|VAX]] [[Instructions per second#Millions of instructions per second (MIPS)|MIPS]]. The 80960KB version is compatible with [[IEEE 754]] standard and can perform up to 4&nbsp;[[Whetstone (benchmark)|MWIPS]]. Both processors are available in 16 and 20&nbsp;MHz using [[CHMOS|CHMOS-III]] technology. Both processors are packaged in [[Pin grid array|132-PGA]]. The 80960KA version is available for US$230 and the 80960KB version is available for US$390 in quantities of 100 respectively.<ref name="Ormsby, Jon 1988, page 9"/>

The i960KA became successful as a low-cost 32-bit processor for the laser-printer market, as well as for early graphics terminals and other embedded applications. Its success paid for future generations, which were without the complex memory sub-system.

===80960CA, 80960CF===
The {{vanchor|i960CA}} was announced in July 1989. It featured a newly designed superscalar RISC core and added an unusual addressable on-chip cache, but lacked an FPU and MMU, as it was intended for high-performance embedded applications. The i960CA is widely considered<ref>{{cite book |last1=Shen |first1=John Paul |last2=Lipasti |first2=Mikko H. |title=Modern Processor Design: Fundamentals of Superscalar Processors |date=2003 |publisher=McGraw Hill |isbn=0-07-282968-0 |page=328 |edition=Beta}}</ref> to have been the first single-chip [[superscalar]] RISC implementation. The C-series included only one ALU, but could dispatch and execute an arithmetic instruction, a memory reference, and a branch instruction at the same time, and sustain two instructions per cycle under certain circumstances. The first versions released ran at 33&nbsp;MHz, and Intel promoted the chip as capable of 66 MIPS. The i960CA microarchitecture was designed in 1987–1988 and formally announced on September 12, 1989.

Later, in May 1992, came the i960CF, which included a larger instruction cache (4 KB instead of 1 KB) and added 1 KB of data cache, but was still without an FPU or MMU.

===80960MX===
The 80960MX is a superscalar implementation of the Extended architecture, executing up to three instructions per clock execution for sustained performance of 25 VAX MIPS.<ref name="intel-military">{{cite book |title=Military and Special Products Handbook |date=1993 |publisher=Intel |pages=11-40 to 11-89 |chapter=i960 MX Processor}}</ref> It implemented the Joint Industrial Avionics Working Group (JIAWG) 32-bit ISA standard. It was originally packaged in a 348 lead ceramic pin grid array and later supplied as a bare die. The i960 MX supports object-oriented programming. A 33rd tag bit distinguished between a 32-bit data word and a 32-bit pointer to memory. This prohibited forged pointers to protected areas of memory.

===80960Jx===
The 80960Jx is a processor for embedded applications. It features a 32-bit multiplexed address/data bus, instruction and data cache, 1K on-chip RAM, interrupt controller, and two independent 32-bit timers. The 80960Jx's testability features included ONCE (on-circuit emulation) mode and boundary scan ([[JTAG]]).

===80960HA, 80960HD, 80960HT===
The 80960Hx processors offered upgraded performance from the Cx variants by offering clock multiplication, larger 16K instruction cache and 4k data cache, and a GMU (Guarded Memory Unit). The HD variant had an internal 2× clock multiplication while the HT version has a 3x clock multiplication, allowing increased performance without external bus speed changes.

===80960VH===
Announced in October 1998, the i960VH Embedded-PCI processor featured a 32-bit 33&nbsp;MHz [[PCI Local Bus|PCI]] bus and 100&nbsp;MHz i960JT processor core. The core also featured 16&nbsp;KB of instruction cache, 4&nbsp;KB of data cache, and 1&nbsp;KB of built-in RAM. Other core features included two 32-bit timers, programmable interrupt controller, [[I²C]] interface, and a two-channel DMA controller.

===80960Rx===
The 80960Rx processors were labeled as I/O Processors and included an implementation of the [[PCI Local Bus|PCI]] Bus (2.1 or 2.2 depending on the variant) as well as a 80960Jx core. These could be used on motherboards to implement on-board PCI device as well as on PCI expansion cards. The RM/RN/RS variants used a JT core with a 3x bus to core multiplication to achieve 100&nbsp;MHz internal clock speeds, while the RD variant used a JF core with 2× multiplication to achieve 66&nbsp;MHz. The RP variant had a JF core that ran at the 33&nbsp;MHz bus speed.