Editing Intel iAPX 432 (section)

==={{Anchor|8800}}Development===
Intel's 432 project started in 1976, a year after the [[8-bit]] [[Intel 8080]] was completed and a year before their 16-bit [[Intel 8086|8086]] project began. The 432 project was initially named the '''8800''',<ref name="i8800"/> as their next step beyond the existing [[Intel 8008]] and [[Intel 8080|8080]] microprocessors.  This became a very big step.  The instruction sets of these 8-bit processors were not very well fitted for typical [[ALGOL|Algol]]-like [[compiled language]]s. However, the major problem was their small native addressing ranges, just 16 KB for 8008 and 64 KB for 8080, far too small for many complex software systems without using some kind of [[bank switching]], [[memory segmentation]], or similar mechanism (which was built into the 8086, a few years later on).  Intel now aimed to build a sophisticated complete system in a few LSI chips, that was functionally equal to or better than the best 32-bit minicomputers and mainframes requiring entire cabinets of older chips.  This system would support multiprocessors, modular expansion, fault tolerance, advanced operating systems, advanced programming languages, very large applications, ultra reliability, and ultra security.  Its architecture would address the needs of Intel's customers for a decade.<ref>{{cite web|title=Intel iAPX 432 - Computer Science 460 - Final Project|author1=David King|author2=Liang Zhou|author3=Jon Bryson|author4=David Dickson|date=April 15, 1999|url=http://www.brouhaha.com/~eric/retrocomputing/intel/iapx432/cs460}}</ref>

The iAPX 432 development team was managed by Bill Lattin, with [[Justin Rattner]] (who would later become CTO of Intel) as the lead engineer<ref>{{cite journal |last1=Mazor |first1=Stanley |title=Intel's 8086 |journal=IEEE Annals of the History of Computing |date=2010 |volume=32 |page=75 |doi=10.1109/MAHC.2010.22 |s2cid=16451604 |url=https://ieeexplore.ieee.org/document/5430762|url-access=subscription }}</ref><ref name="Mayer2012"></ref><ref>{{cite book |title=Defining Intel: 25 years / 25 events |date=1993 |publisher=Intel |page=14 |url=https://www.intel.com/assets/pdf/general/25yrs.pdf}}</ref> (although one source<ref name="dvorak"/> states that [[Fred Pollack]] was the lead engineer). Initially the team worked from Santa Clara, but in March 1977 Lattin and his team of 17 engineers moved to Intel's new site in Portland.<ref name="Mayer2012">{{cite book|author=Heike Mayer|title=Entrepreneurship and Innovation in Second Tier Regions|url=https://books.google.com/books?id=OgUJJPuDvfQC&pg=PA100|year=2012|publisher=Edward Elgar Publishing|isbn=978-0-85793-869-5|pages=100–101}}</ref> Pollack later specialized in [[superscalar]]ity and became the lead architect of the i686 chip [[Intel Pentium Pro]].<ref name="dvorak"/>

It soon became clear that it would take several years and many engineers to design all this.  And it would similarly take several years of further progress in [[Moore's Law]], before improved [[Semiconductor device fabrication|chip manufacturing]] could fit all this into a few dense chips.  Meanwhile, Intel urgently needed a simpler interim product to meet the immediate competition from [[Motorola]], [[Zilog]], and [[National Semiconductor]]. So Intel began a rushed project to design the 8086 as a low-risk incremental evolution from the 8080, using a separate design team.  The mass-market 8086 shipped in 1978.

The 8086 was designed to be backward-compatible with the 8080 in the sense that 8080 [[assembly language]] could be mapped on to the 8086 architecture using a special [[assembler (computing)|assembler]]. Existing 8080 assembly [[source code]] (albeit no [[executable code]]) was thereby made [[upward compatible]] with the new 8086 to a degree. In contrast, the 432 had no software compatibility or migration requirements.  The architects had total freedom to do a novel design from scratch, using whatever techniques they guessed  would be best for large-scale systems and software.  They applied fashionable computer science concepts from universities, particularly [[capability-based addressing|capability machines]], object-oriented programming, high-level CISC machines, Ada, and densely encoded instructions.  This ambitious mix of novel features made the chip larger and more complex. The chip's complexity limited the clock speed and lengthened the design schedule.

The core of the design — the main processor — was termed the General Data Processor ('''GDP''') and built as two [[integrated circuit]]s: one (the 43201) to [[Fetch-execute cycle|fetch and decode]] instructions, the other (the 43202) to execute them. Most systems would also include the 43203 Interface Processor ('''IP''') which operated as a [[channel controller]] for [[Input/output|I/O]], and an Attached Processor ('''AP'''), a conventional Intel 8086 which provided "processing power in the I/O subsystem".<ref name=Intel81 />

These were some of the largest {{Clarify|IC|date=October 2012}} designs of the era. The two-chip GDP had a combined count of approximately 97,000&nbsp;[[transistor]]s{{Citation needed|reason=Another source states 159,000 transistors|date=April 2023}} while the single chip IP had approximately 49,000. By comparison, the [[Motorola 68000]] (introduced in 1979) had approximately 40,000&nbsp;transistors.{{Citation needed|reason=Other (unreliable) sources say the 68000 had about 70,000 transistors|date=September 2018}}

In 1983, Intel released two additional integrated circuits for the iAPX 432 Interconnect Architecture: the 43204 Bus Interface Unit ('''BIU''') and 43205 Memory Control Unit ('''MCU'''). These chips allowed for nearly glueless multiprocessor systems with up to 63&nbsp;nodes.