Editing Itanium (section)

==== Inception: 1989–1994 ====
In 1989, HP started to research an architecture that would exceed the expected limits of the [[reduced instruction set computer]] (RISC) architectures caused by the great increase in complexity needed for executing multiple [[instructions per cycle]] due to the need for dynamic [[Data dependency|dependency]] checking and precise [[exception handling]].{{Efn|The size of the needed dependency-checking circuitry increases [[Quadratic growth|quadratically]] with the issue width.<ref name="simplicity"/><ref name="Understanding_EPIC"/>}} HP hired [[Bob Rau]] of [[Cydrome]] and [[Josh Fisher]] of [[Multiflow]], the pioneers of [[very long instruction word]] (VLIW) computing. One VLIW instruction word can contain several independent [[instruction (computer science)|instructions]], which can be executed in parallel without having to evaluate them for independence. A [[compiler]] must attempt to find [[Instruction-level parallelism|valid combinations of instructions that can be executed at the same time]], effectively performing the instruction scheduling that conventional [[superscalar processor]]s must do in hardware at runtime.

HP researchers modified the classic VLIW into a new type of architecture, later named [[Explicitly Parallel Instruction Computing]] (EPIC), which differs by: having template bits which show which instructions are independent inside and between the bundles of three instructions, which enables the explicitly parallel execution of multiple bundles and increasing the processors' [[Wide-issue|issue width]] without the need to recompile; by [[Predication (computer architecture)|predication]] of instructions to reduce the need for [[Branch (computer science)|branches]]; and by full interlocking to eliminate the [[delay slot]]s. In EPIC the assignment of [[execution unit]]s to instructions and the timing of their issuing can be decided by hardware, unlike in the classic VLIW. HP intended to use these features in PA-WideWord, the planned successor to their [[PA-RISC]] ISA. EPIC was intended to provide the best balance between the efficient use of silicon area and electricity, and general-purpose flexibility.<ref name="Understanding_EPIC">{{cite web |last1=Smotherman |first1=Mark |title=Understanding EPIC Architectures and Implementations |url=https://people.computing.clemson.edu/~mark/464/acmse_epic.pdf |publisher=[[Clemson University]] |access-date=5 June 2022}}</ref><ref name="HP_Labs">{{cite web
 | url=https://www.hpl.hp.com/news/2001/apr-jun/itanium.html
 | title=Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture
 | access-date=March 23, 2007
 | date=June 2001
 | work=[[HP Labs]]
 }}</ref> In 1993 HP held an internal competition to design the best (simulated) microarchitectures of a RISC and an EPIC type, led by Jerry Huck and [[Rajiv Gupta (technocrat)|Rajiv Gupta]] respectively. The EPIC team won, with over double the simulated performance of the RISC competitor.<ref name="nyt_merced">{{cite web |last1=Markoff |first1=John |title=Inside Intel, The Future is Riding on the Merced Chip |url=https://archive.org/details/TheJerusalemPost1998IsraelEnglish/Apr%2006%201998%2C%20The%20Jerusalem%20Post%2C%20%2319898%2C%20Israel%20%28en%29/page/n12/mode/1up |publisher=[[The New York Times]], republised by [[The Jerusalem Post]] |date=5 April 1998}}</ref>

At the same time Intel was also looking for ways to make better ISAs. In 1989 Intel had launched the [[Intel i860|i860]], which it marketed for workstations, servers, and [[Intel iPSC#iPSC/860|iPSC]] and [[Intel Paragon|Paragon]] supercomputers. It differed from other RISCs by being able to switch between the normal single instruction per cycle mode, and a mode where pairs of instructions are explicitly defined as parallel so as to execute them in the same cycle without having to do dependency checking. Another distinguishing feature were the instructions for an exposed floating-point pipeline, that enabled the tripling of throughput compared to the conventional floating-point instructions. Both of these features were left largely unused because compilers didn't support them, a problem that later challenged Itanium too. Without them, i860's parallelism (and thus performance) was no better than other RISCs, so it failed in the market. Itanium would adopt a more flexible form of explicit parallelism than i860 had.<ref>{{cite web |last1=DeMone |first1=Paul |title=Intel's History Lesson |url=https://www.realworldtech.com/intel-history-lesson/ |website=Real World Tech |date=25 January 2000}}</ref>

In November 1993 HP approached Intel, seeking collaboration on an innovative future architecture.<ref name="countdown">{{cite web |last1=DeMone |first1=Paul |title=Countdown to IA-64 |url=https://www.realworldtech.com/countdown-to-ia64/ |website=Real World Tech |date=14 March 2001}}</ref>{{refn|{{cite web |last1=Alpert |first1=Donald |title=Intel Itanium Processor (Merced) |url=https://camelback-comparch.com/about/technical-highlights/#merced |date=July 2003}} Alpert was the chief architect of the original P7 and the top engineering manager of Merced<ref>{{cite web |last1=Smotherman |first1=Mark |title=Who are the Computer Architects? |url=https://people.computing.clemson.edu/~mark/architects.html |publisher=[[Clemson University]] }} See the sections "Independence architecture" and "Wintel".</ref>}} At the time Intel was looking to extend x86 to 64 bits in a processor codenamed P7, which they found challenging.<ref>{{cite web |last1=DeMone |first1=Paul |title=What's Up With Willamette? (Part 1) |url=https://www.realworldtech.com/willamette-basics/ |website=Real World Tech |date=3 March 2000}}</ref> Later Intel claimed that four different design teams had explored 64-bit extensions, but each of them concluded that it was not economically feasible.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel takes slow road to 64-bit PC chips |url=https://www.cnet.com/tech/tech-industry/intel-takes-slow-road-to-64-bit-pc-chips/ |website=[[CNET]] |date=21 February 2003}}</ref> At the meeting with HP, Intel's engineers were impressed when Jerry Huck and [[Rajiv Gupta (technocrat)|Rajiv Gupta]] presented the PA-WideWord architecture they had designed to replace [[PA-RISC]]. "When we saw WideWord, we saw a lot of things we had only been looking at doing, already in their full glory", said Intel's [[John Crawford (engineer)|John Crawford]], who in 1994 became the chief architect of Merced, and who had earlier argued against extending the x86 with P7. HP's Gupta recalled: "I looked Albert Yu [Intel's general manager for microprocessors] in the eyes and showed him we could run circles around [[PowerPC]], that we could kill PowerPC, that we could kill the x86."<ref name="gambles"/> Soon Intel and HP started conducting in-depth technical discussions at an HP office, where each side had six{{Refn|<ref name="countdown"/><ref name="birth">{{cite web |last1=Britt |first1=Russ |title=The birth of a new processor |url=https://www.edn.com/the-birth-of-a-new-processor/ |website=[[EDN (magazine)|EDN]] |date=1 January 2000}}</ref> (The {{Define|ACM|architecture, compilers, microarchitecture}} committee with 5 people from each side<ref>{{cite web |last1=Smotherman |first1=Mark |title=Historical background for EPIC instruction set architectures |url=https://people.computing.clemson.edu/~mark/epic.html |publisher=[[Clemson University]] |access-date=3 June 2022}}</ref> was probably a different entity.)}} engineers who exchanged and discussed both companies' confidential architectural research. They then decided to use not only PA-WideWord, but also the more experimental [[HP Labs]] PlayDoh as the source of their joint future architecture.<ref name="simplicity">{{cite web |last1=DeMone |first1=Paul |title=HP's Struggle For Simplicity Ends at Intel |url=https://www.realworldtech.com/hp-intel-itanium/ |website=Real World Tech |date=27 October 1999}}</ref><ref>{{cite web |last1=Kathail |first1=Vinod |last2=Schlansker |first2=Michael S. |last3=Rau |first3=B. Ramakrishna |title=HPL-PD Architecture Specification: Version 1.1 |url=https://www.hpl.hp.com/techreports/93/HPL-93-80R1.pdf |publisher=[[HP Labs|HP Laboratories]] |access-date=2023-07-05 |archive-date=2024-02-04 |archive-url=https://web.archive.org/web/20240204063521/https://www.hpl.hp.com/techreports/93/HPL-93-80R1.pdf |url-status=dead }}</ref> Convinced of the superiority of the new project, in 1994 Intel canceled their existing plans for P7.

In June 1994 Intel and HP announced their joint effort to make a new ISA that would adopt ideas of Wide Word and VLIW. Yu declared: "If I were competitors, I'd be really worried. If you think you have a future, you don't."<ref name="gambles">{{cite web |last1=Hamilton |first1=David |title=Intel gambles with Itanium |url=https://www.zdnet.com/article/intel-gambles-with-itanium/ |website=[[ZDNet]] |date=28 May 2001}}</ref> On P7's future, Intel said the alliance would impact it, but "it is not clear" whether it would "fully encompass the new architecture".<ref>{{cite web |last1=Hecht |first1=Jeff |title=Technology: Intel opts for simpler, speedier chips |url=https://www.newscientist.com/article/mg14219303-300-technology-intel-opts-for-simpler-speedier-chips/ |website=[[New Scientist]] |date=18 June 1994}}</ref><ref>{{cite web |last1=Bozman |first1=Jean S. |title=Chip alliance shakes ground |url=https://books.google.com/books?id=QZtKFFB8weQC&pg=PA12 |website=[[Computerworld]] |date=13 June 1994}} David House had approved the project, but later severely criticized it.</ref>
Later the same month, Intel said that some of the first features of the new architecture would start appearing on Intel chips as early as the P7, but the full version would appear sometime later.<ref>{{cite web |last1=Babcock |first1=Charles |title=Silicon marriage: HP/Intel venture |url=https://books.google.com/books?id=QtpyKsPTNwkC&pg=PA6 |website=[[Computerworld]] |date=25 July 1994}}</ref>
In August 1994 [[EE Times]] reported that Intel told investors that P7 was being re-evaluated and possibly canceled in favor of the HP processor. Intel immediately issued a clarification, saying that P7 is still being defined, and that HP may contribute to its architecture. Later it was confirmed that the P7 codename had indeed passed to the HP-Intel processor. By early 1996 Intel revealed its new codename, ''Merced''.<ref>{{cite web |last1=DeMone |first1=Paul |title=Countdown to IA-64 |url=https://www.realworldtech.com/countdown-to-ia64/ |website=Real World Tech |date=14 March 2001}} Has a typo (P'''5''') in the graphic.</ref><ref>{{cite web |last1=Crothers |first1=Brooke |title=Intel aims to bring multimedia to the masses |url=https://books.google.com/books?id=zD4EAAAAMBAJ&pg=PA8 |website=[[InfoWorld]] |date=29 January 1996}}</ref>

HP believed that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so it partnered with Intel in 1994 to develop the IA-64 architecture, derived from EPIC. Intel was willing to undertake the very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of enterprise systems manufacturers. HP and Intel initiated a large joint development effort with a goal of delivering the first product, Merced, in 1998.<ref name="HP_Labs"/>