Editing Logical effort (section)

==Multistage logic networks==
A major advantage of the method of logical effort is that it can quickly be extended to circuits composed of multiple stages.  The total normalized path delay ''D'' can be expressed in terms of an overall '''path effort''', ''F'', and the '''path parasitic delay''' ''P'' (which is the sum of the individual parasitic delays):

:<math>D = NF^{1/N} + P</math>

The path effort is expressed in terms of the '''path logical effort''' ''G'' (the product of the individual logical efforts of the gates), and the '''path electrical effort''' ''H'' (the ratio of the load of the path to its input capacitance).

For paths where each gate drives only one additional gate (i.e. the next gate in the path),
:<math>F = GH</math>

However, for circuits that branch, an additional '''branching effort''', ''b'', needs to be taken into account; it is the ratio of total capacitance being driven by the gate to the capacitance on the path of interest:
:<math>b = \frac{C_{onpath} + C_{offpath}}{C_{onpath}}</math>

This yields a '''path branching effort''' ''B'' which is the product of the individual stage branching efforts; the total path effort is then
:<math>F = GHB</math>

It can be seen that ''b'' = 1 for gates driving only one additional gate, fixing ''B'' = 1 and causing the formula to reduce to the earlier non-branching version.

===Minimum delay===
It can be shown that in multistage logic networks, the minimum possible delay along a particular path can be achieved by designing the circuit such that the stage efforts are equal.  For a given combination of gates and a known load, ''B'', ''G'', and ''H'' are all fixed causing ''F'' to be fixed; hence the individual gates should be sized such that the individual stage efforts are
:<math>f = F^{1/N}</math>
where ''N'' is the number of stages in the circuit.