Editing Loop nest optimization (section)

==Tiling size==
It is not always easy to decide what value of tiling size is optimal for one loop because it demands an accurate estimate of accessed array regions in the loop and the cache size of the target machine. The order of loop nests ([[loop interchange]]) also plays an important role in achieving better cache performance. Explicit blocking requires choosing a tile size based on these factors. By contrast, [[cache-oblivious algorithm]]s are designed to make efficient use of cache without explicit blocking.