Editing MIPS architecture (section)

== Versions ==

=== MIPS I ===

MIPS is a [[load/store architecture]] (also known as a ''register-register architecture''); except for the [[load/store instructions]] used to access [[Computer memory|memory]], all instructions operate on the registers.

==== Registers ====

MIPS I has thirty-two 32-bit general-purpose registers (GPR). Register {{mono|$0}} is hardwired to zero and writes to it are discarded. Register {{mono|$31}} is the [[link register]]. For integer multiplication and division instructions, which run asynchronously from other instructions, a pair of 32-bit registers, ''HI'' and ''LO'', are provided. There is a small set of instructions for copying data between the general-purpose registers and the HI/LO registers.

The program counter has 32 bits. The two low-order bits always contain zero since MIPS I instructions are 32 bits long and are aligned to their natural word boundaries.

==== Instruction formats ====

Instructions are divided into three types: R (register), I (immediate), and J (jump). Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers,<ref name="Harris Harris 2013 pp. 294–369">{{cite book | last1=Harris | first1=David Money | last2=Harris | first2=Sarah L. | title=Digital Design and Computer Architecture | chapter=Architecture | publisher=Elsevier | year=2013 | doi=10.1016/b978-0-12-394424-5.00006-9 | pages=294–369 | isbn=9780123944245 | quote=R-type is short for register-type. R-type instructions use three registers as operands: two as sources, and one as a destination.}}</ref> a shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target.<ref name=Price1995/>{{rp|A-174}}

The following are the three formats used for the core instruction set:

{| class="wikitable"
|-
! Type || colspan=6| -31- &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; format (bits) &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; -0-
|- align=center
| '''R''' || opcode (6) || rs (5) || rt (5) || rd (5) || shamt (5) || funct (6)
|- align=center
| '''I''' || opcode (6) || rs (5) || rt (5) ||colspan=3| immediate (16)
|- align=center
| '''J''' || opcode (6) ||colspan=5| address (26)
|}

==== CPU instructions ====

MIPS I has instructions that load and store 8-bit bytes, 16-bit halfwords, and 32-bit words. Only one [[addressing mode]] is supported: base + displacement. Since MIPS I is a 32-bit architecture, loading quantities fewer than 32 bits requires the datum to be either sign-extended or zero-extended to 32 bits. The load instructions suffixed by "unsigned" perform zero extension; otherwise sign extension is performed. Load instructions source the base from the contents of a GPR (rs) and write the result to another GPR (rt). Store instructions source the base from the contents of a GPR (rs) and the store data from another GPR (rt). All load and store instructions compute the memory address by summing the base with the sign-extended 16-bit immediate. MIPS I requires all memory accesses to be aligned to their natural word boundaries, otherwise an exception is signaled. To support efficient unaligned memory accesses, there are load/store word instructions suffixed by "left" or "right". All load instructions are followed by a [[load delay slot]]. The instruction in the load delay slot cannot use the data loaded by the load instruction. The load delay slot can be filled with an instruction that is not dependent on the load; a NOP is substituted if such an instruction cannot be found.

MIPS I has instructions to perform addition and subtraction. These instructions source their operands from two GPRs (rs and rt), and write the result to a third GPR (rd). Alternatively, addition can source one of the operands from a 16-bit immediate (which is sign-extended to 32 bits). The instructions for addition and subtraction have two variants: by default, an exception is signaled if the result overflows; instructions with the "unsigned" suffix do not signal an exception. The overflow check interprets the result as a 32-bit two's complement integer. MIPS I has instructions to perform [[bitwise operation|bitwise]] logical AND, OR, XOR, and NOR. These instructions source their operands from two GPRs and write the result to a third GPR. The AND, OR, and XOR instructions can alternatively source one of the operands from a 16-bit immediate (which is zero-extended to 32 bits). The "Set on ''relation''" instructions write one or zero to the destination register if the specified relation is true or false. These instructions source their operands from two GPRs or one GPR and a 16-bit immediate (which is sign-extended to 32 bits), and write the result to a third GPR. By default, the operands are interpreted as signed integers. The variants of these instructions that are suffixed with "unsigned" interpret the operands as unsigned integers (even those that source an operand from the sign-extended 16-bit immediate).

The Load Upper Immediate instruction copies the 16-bit immediate into the high-order 16 bits of a GPR. It is used in conjunction with the Or Immediate instruction to load a 32-bit immediate into a register.

MIPS I has instructions to perform left and right logical shifts and right arithmetic shifts. The operand is obtained from a GPR (rt), and the result is written to another GPR (rd). The shift distance is obtained from either a GPR (rs) or a 5-bit "shift amount" (the "sa" field).

MIPS I has instructions for signed and unsigned integer multiplication and division. These instructions source their operands from two GPRs and write their results to a pair of 32-bit registers called HI and LO, since they may execute separately from (and concurrently with) the other CPU instructions. For multiplication, the high- and low-order halves of the 64-bit product is written to HI and LO (respectively). For division, the quotient is written to LO and the remainder to HI. To access the results, a pair of instructions (Move from HI and Move from LO) is provided to copy the contents of HI or LO to a GPR. These instructions are interlocked: reads of HI and LO do not proceed past an unfinished arithmetic instruction that will write to HI and LO. Another pair of instructions (Move to HI or Move to LO) copies the contents of a GPR to HI and LO. These instructions are used to restore HI and LO to their original state after exception handling. Instructions that read HI or LO must be separated by two instructions that do not write to HI or LO.

All MIPS I control flow instructions are followed by a [[branch delay slot]]. Unless the branch delay slot is filled by an instruction performing useful work, a NOP is substituted. MIPS I branch instructions compare the contents of a GPR (rs) against zero or another GPR (rt) as signed integers and branch if the specified condition is true. Control is transferred to the address computed by shifting the 16-bit offset left by two bits, sign-extending the 18-bit result, and adding the 32-bit sign-extended result to the sum of the program counter (instruction address) and 8<sub>10</sub>. Jumps have two versions: absolute and register-indirect. Absolute jumps ("Jump" and "Jump and Link") compute the address to which control is transferred by shifting the 26-bit instr_index left by two bits and concatenating the 28-bit result with the four high-order bits of the address of the instruction in the branch delay slot. Register-indirect jumps transfer control to the instruction at the address sourced from a GPR (rs). The address sourced from the GPR must be word-aligned, else an exception is signaled after the instruction in the branch delay slot is executed. Branch and jump instructions that link (except for "Jump and Link Register") save the return address to GPR 31. The "Jump and Link Register" instruction permits the return address to be saved to any writable GPR.

MIPS I has two instructions for software to signal an exception: System Call and Breakpoint. System Call is used by user mode software to make kernel calls; and Breakpoint is used to transfer control to a debugger via the kernel's exception handler. Both instructions have a 20-bit Code field that can contain operating environment-specific information for the exception handler.

MIPS has 32 floating-point registers. Two registers are paired for double precision numbers. Odd numbered registers cannot be used for arithmetic or branching, just as part of a double precision register pair, resulting in 16 usable registers for most instructions (moves/copies and loads/stores were not affected).

Single precision is denoted by the .s suffix, while double precision is denoted by the .d suffix.

=== MIPS II ===

MIPS II removed the load delay slot<ref name=Sweetman1999/>{{rp|41}} and added several sets of instructions. For shared-memory multiprocessing, the ''Synchronize Shared Memory'', ''Load Linked Word'', and ''Store Conditional Word'' instructions were added.<ref name="mips-ll-sc">{{Cite web |url=https://www.cs.auckland.ac.nz/compsci313s2c/resources/MIPSLLSC.pdf#page=9 |title=APPLICATION NOTE MIPS R4000 Synchronization Primitives |page=5 |accessdate=2023-12-27 |archive-date=December 27, 2023 |archive-url=https://web.archive.org/web/20231227143936/https://www.cs.auckland.ac.nz/compsci313s2c/resources/MIPSLLSC.pdf#page=9 |url-status=live }}</ref> A set of Trap-on-Condition instructions were added. These instructions caused an exception if the evaluated condition is true. All existing branch instructions were given ''branch-likely'' versions that executed the instruction in the branch delay slot only if the branch is taken.<ref name=Sweetman1999/>{{rp|40}} These instructions improve performance in certain cases by allowing useful instructions to fill the branch delay slot.<ref name=Sweetman1999/>{{rp|212}} Doubleword load and store instructions for COP1–3 were added. Consistent with other memory access instructions, these loads and stores required the doubleword to be naturally aligned.

The instruction set for the floating point coprocessor also had several instructions added to it. An IEEE 754-compliant floating-point square root instruction was added. It supported both single- and double-precision operands. A set of instructions that converted single- and double-precision floating-point numbers to 32-bit words were added. These complemented the existing conversion instructions by allowing the IEEE rounding mode to be specified by the instruction instead of the Floating Point Control and Status Register.

=== MIPS III ===

MIPS III is a [[backwards-compatible]] extension of MIPS II that added support for [[64-bit]] memory addressing and integer operations. The 64-bit data type is called a doubleword, and MIPS III extended the general-purpose registers, HI/LO registers, and program counter to 64 bits to support it. New instructions were added to load and store doublewords, to perform integer addition, subtraction, multiplication, division, and shift operations on them, and to move doubleword between the GPRs and HI/LO registers. For shared-memory multiprocessing, the ''Load Linked Double Word'', and ''Store Conditional Double Word'' instructions were added.<ref name="mips-ll-sc"/> Existing instructions originally defined to operate on 32-bit words were redefined, where necessary, to sign-extend the 32-bit results to permit words and doublewords to be treated identically by most instructions. Among those instructions redefined was ''Load Word''. In MIPS III it sign-extends words to 64 bits. To complement ''Load Word'', a version that zero-extends was added.

The R instruction format's inability to specify the full shift distance for 64-bit shifts (its 5-bit shift amount field is too narrow to specify the shift distance for doublewords) required MIPS III to provide three 64-bit versions of each MIPS I shift instruction. The first version is a 64-bit version of the original shift instructions, used to specify constant shift distances of 0–31 bits. The second version is similar to the first, but adds 32<sub>10</sub> the shift amount field's value so that constant shift distances of 32–63 bits can be specified. The third version obtains the shift distance from the six low-order bits of a GPR.

MIPS III added a ''supervisor'' privilege level in between the existing kernel and user privilege levels. This feature only affected the implementation-defined System Control Processor (Coprocessor 0).

MIPS III removed the Coprocessor 3 (CP3) support instructions, and reused its opcodes for the new doubleword instructions. The remaining coprocessors gained instructions to move doublewords between coprocessor registers and the GPRs. The floating general registers (FGRs) were extended to 64 bits and the requirement for instructions to use even-numbered register only was removed. This is incompatible with earlier versions of the architecture; a bit in the floating-point control/status register is used to operate the MIPS III floating-point unit (FPU) in a MIPS I- and II-compatible mode. The floating-point control registers were not extended for compatibility. The only new floating-point instructions added were those to copy doublewords between the CPU and FPU convert single- and double-precision floating-point numbers into doubleword integers and vice versa.

=== MIPS IV ===

MIPS IV is the fourth version of the architecture. It is a superset of MIPS III and is compatible with all existing versions of MIPS.<ref>{{cite book|url=https://www.cs.cmu.edu/afs/cs/academic/class/15740-f97/public/doc/mips-isa.pdf|title=MIPS IV Instruction Set|edition=Revision 3.2|date=September 1995|publisher=[[MIPS Technologies]]|access-date=August 24, 2022|archive-date=November 27, 2022|archive-url=https://web.archive.org/web/20221127225045/http://www.cs.cmu.edu/afs/cs/academic/class/15740-f97/public/doc/mips-isa.pdf|url-status=live}}</ref>{{rp|page=A{{hyp}}1}} MIPS IV was designed to mainly improve floating-point (FP) performance. To improve access to operands, an indexed [[addressing mode]] (base + index, both sourced from GPRs) for FP loads and stores was added, as were prefetch instructions for performing memory prefetching and specifying cache hints (these supported both the base + offset and base + index addressing modes).

MIPS IV added several features to improve instruction-level parallelism. To alleviate the bottleneck caused by a single condition bit, seven condition code bits were added to the floating-point control and status register, bringing the total to eight. FP comparison and branch instructions were redefined so they could specify which condition bit was written or read (respectively); and the delay slot in between an FP branch that read the condition bit written to by a prior FP comparison was removed. Support for [[Branch predication|partial predication]] was added in the form of conditional move instructions for both GPRs and FPRs; and an implementation could choose between having precise or imprecise exceptions for IEEE 754 traps.

MIPS IV added several new FP arithmetic instructions for both single- and double-precision FPNs: fused-multiply add or subtract, reciprocal, and reciprocal square-root. The FP fused-multiply add or subtract instructions perform either one or two roundings (it is implementation-defined), to exceed or meet IEEE 754 accuracy requirements (respectively). The FP reciprocal and reciprocal square-root instructions do not comply with IEEE 754 accuracy requirements, and produce results that differ from the required accuracy by one or two units of last place (it is implementation defined). These instructions serve applications where instruction latency is more important than accuracy.

=== MIPS V ===

MIPS V added a new data type, the Paired Single (PS), which consisted of two single-precision (32-bit) floating-point numbers stored in the existing 64-bit floating-point registers. Variants of existing floating-point instructions for arithmetic, compare and conditional move were added to operate on this data type in a SIMD fashion. New instructions were added for loading, rearranging and converting PS data.<ref name=Sweetman1999/>{{rp|426–429}} It was the first instruction set to exploit floating-point SIMD with existing resources.<ref name="MPR:1996-11-18"/>

=== MIPS32/MIPS64 ===

The first release of MIPS32, based on MIPS II, added conditional moves, [[Instruction prefetch|prefetch instructions]], and other features from the R4000 and R5000 families of 64-bit processors.<ref name="mips32-and-mips64"/> The first release of MIPS64 adds a MIPS32 mode to run 32-bit code.<ref name="mips32-and-mips64"/> The MUL and MADD ([[multiply-add]]) instructions, previously available in some implementations, were added to the MIPS32 and MIPS64 specifications, as were [[cache control instruction]]s.<ref name="mips32-and-mips64"/> For the purpose of cache control, both <code>SYNC</code> and <code>SYNCI</code> instructions were prepared.<ref>{{Cite web |url=https://training.mips.com/basic_mips/PDF/Instruction_Set.pdf |title=MIPS instruction set R5 |page=59-62 |accessdate=2023-12-15 |archive-date=December 15, 2023 |archive-url=https://web.archive.org/web/20231215041747/https://training.mips.com/basic_mips/PDF/Instruction_Set.pdf |url-status=live }}</ref><ref>{{Cite web |url=https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00605-2B-CMPCOHERE-AFP-01.01.pdf |title=MIPS® Coherence Protocol Specification, Revision 01.01 |page=26,25,57 |accessdate=2023-12-15 |archive-date=September 4, 2018 |archive-url=https://web.archive.org/web/20180904050625/https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00605-2B-CMPCOHERE-AFP-01.01.pdf |url-status=live }}</ref>

MIPS32/MIPS64 Release 6 in 2014 added the following:<ref>{{cite web|url=https://imgtec.com/mips/architectures/mips32/|title=MIPS – Market-leading RISC CPU IP processor solutions|website=imgtec.com|url-status=dead|archive-url=https://web.archive.org/web/20160309061723/https://imgtec.com/mips/architectures/mips32/|archive-date=March 9, 2016|access-date=February 11, 2016}}</ref>
* a new family of branches with no delay slot:
** unconditional branches (BC) and branch-and-link (BALC) with a 26-bit offset,
** conditional branch on zero/non-zero with a 21-bit offset,
** full set of signed and unsigned conditional branches compare between two registers (e.g. BGTUC) or a register against zero (e.g. BGTZC),
** full set of branch-and-link which compare a register against zero (e.g. BGTZALC).
* index jump instructions with no delay slot designed to support large absolute addresses.
* instructions to load 16-bit immediates at bit position 16, 32 or 48, allowing to easily generate large constants.
* PC-relative load instructions, as well as address generation with large (PC-relative) offsets.
* bit-reversal and byte-alignment instructions (previously only available with the DSP extension).
* multiply and divide instructions redefined so that they use a single register for their result).
* instructions generating truth values now generate all zeroes or all ones instead of just clearing/setting the 0-bit,
* instructions using a truth value now only interpret all-zeroes as false instead of just looking at the 0-bit.

Removed infrequently used instructions:
* some conditional moves
* ''branch likely'' instructions (deprecated in previous releases).
* integer overflow trapping instructions with 16-bit immediate
* integer accumulator instructions (together HI/LO registers, moved to the DSP Application-Specific Extension)
* unaligned load instructions (LWL and LWR), (requiring that most ordinary loads and stores support misaligned access, possibly via trapping and with the addition of a new instruction (BALIGN))

Reorganized the instruction encoding, freeing space for future expansions.

=== microMIPS ===

The microMIPS32/64 architectures are supersets of the MIPS32 and MIPS64 architectures (respectively) designed to replace the [[#MIPS16|MIPS16e]] [[#Application-Specific_Extensions|application-specific extension]] (ASE). A disadvantage of MIPS16e is that it requires a mode switch before any of its 16-bit instructions can be processed. microMIPS adds versions of the most-frequently used 32-bit instructions that are encoded as 16-bit instructions. This allows programs to intermix 16- and 32-bit instructions without having to switch modes. microMIPS was introduced alongside of MIPS32/64 Release 3, and each subsequent release of MIPS32/64 has a corresponding microMIPS32/64 version. A processor may implement microMIPS32/64 or both microMIPS32/64 and its corresponding MIPS32/64 subset. Starting with MIPS32/64 Release 6, support for MIPS16e ended, and microMIPS is the only form of code compression in MIPS.