Editing MMX (instruction set) (section)

===Technical details===
[[File:Pentium II.jpg|thumb|Pentium II processor with MMX technology]]
MMX defines eight [[processor register]]s, named MM0 through MM7, and operations that operate on them. Each register is 64 bits wide and can be used to hold either 64-bit [[integer]]s, or multiple smaller integers in a "packed" format: one instruction can then be applied to two 32-bit integers, four 16-bit integers, or eight 8-bit integers at once.<ref name="MMXARCH">{{cite journal |last=Pfeiffer |first=Joseph J. Jr. |year=1997 |url=https://www.cs.nmsu.edu/~pfeiffer/classes/473/notes/micro.pdf |journal=Intel Technology Journal |title=MMX Microarchitecture of Pentium Processors With MMX Technology and Pentium II Microprocessors |access-date=September 1, 2017 |url-status=dead |archive-url=https://web.archive.org/web/20110112073044/http://www.cs.nmsu.edu/~pfeiffer/classes/473/notes/micro.pdf |archive-date=January 12, 2011}}</ref>

MMX provides only integer operations. When originally developed, for the [[Intel i860]], the use of integer math made sense (both 2D and 3D calculations required it), but as graphics cards that did much of this became common, integer [[SIMD]] in the CPU became somewhat redundant for graphical applications.{{Citation needed|date=January 2016}} Alternatively, the [[saturation arithmetic]] operations in MMX could{{vague|date=January 2016}} significantly speed up some [[digital signal processing]] applications.{{Citation needed|date=January 2016}}

To avoid compatibility problems with the [[context switch]] mechanisms in existing operating systems, the MMX registers are aliases for the existing [[x87]] [[floating-point unit]] (FPU) registers, which context switches would already save and restore. Unlike the x87 registers, which behave like a [[Stack (abstract data type)|stack]], the MMX registers are each directly addressable (random access).

Any operation involving the floating-point stack might also affect the MMX registers and vice versa, so this aliasing makes it difficult to work with floating-point and SIMD operations in the same program.<ref name="conte">{{cite conference |last1=Conte |first1=G. |last2=Tommesani |first2=S. |last3=Zanichelli |first3=F. |year=2000 |title=The long and winding road to high-performance image processing with MMX/SSE |conference=Proceedings of IEEE International Workshop on Computer Architectures for Machine Perception |url=https://air.unipr.it/retrieve/handle/11381/2297671/6288/camp2000.pdf |archive-url=https://web.archive.org/web/20160128221609/https://air.unipr.it/retrieve/handle/11381/2297671/6288/camp2000.pdf |url-status=dead |archive-date=2016-01-28}}</ref> To maximize performance, software often used the processor exclusively in one mode or the other, deferring the relatively slow switch between them as long as possible.

Each 64-bit MMX register corresponds to the [[Significand|mantissa]] part of an 80-bit x87 register. The upper 16 bits of the x87 registers thus go unused in MMX, and these bits are all set to ones, making them ''Not a Number'' ([[NaN]]) data types, or infinities in the floating-point representation. This can be used by software to decide whether a given register's content is intended as floating-point or SIMD data.