Editing Moore's law (section)

== Major enabling factors ==
{{See also|List of semiconductor scale examples|Transistor count}}
[[File:NAND scaling timeline.png|thumb|upright=2|The trend of [[MOSFET scaling]] for [[NAND flash]] memory allows [[transistor count|the doubling]] of [[floating-gate MOSFET]] components manufactured in the same wafer area in less than 18 months.|alt=A semi-log plot of NAND flash design rule dimensions in nanometers against dates of introduction. The downward linear regression indicates an exponential decrease in feature dimensions over time.]]

Numerous innovations by scientists and engineers have sustained Moore's law since the beginning of the IC era. Some of the key innovations are listed below, as examples of breakthroughs that have advanced integrated circuit and [[semiconductor device fabrication]] technology, allowing transistor counts to grow by more than seven orders of magnitude in less than five decades.
* [[Integrated circuit]] (IC): The ''raison d'être'' for Moore's law. The [[germanium]] [[Hybrid integrated circuit|hybrid IC]] was invented by [[Jack Kilby]] at [[Texas Instruments]] in 1958,<ref>Kilby, Jack, "Miniaturized electronic circuits", {{patent|US|3138743}}, issued June 23, 1964 (filed February 6, 1959).</ref> followed by the invention of the [[silicon]] [[Monolithic integrated circuit|monolithic IC]] chip by [[Robert Noyce]] at Fairchild Semiconductor in 1959.<ref>Noyce, Robert, "Semiconductor device-and-lead structure", {{patent|US|2981877}}, issued April 25, 1961 (filed July 30, 1959).</ref>
* [[Complementary metal–oxide–semiconductor]] (CMOS): The CMOS process was invented by [[Chih-Tang Sah]] and [[Frank Wanlass]] at Fairchild Semiconductor in 1963.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |access-date=6 July 2019 |website=[[Computer History Museum]]}}</ref><ref name="sah">{{cite conference |last1=Sah |first1=Chih-Tang |author1-link=Chih-Tang Sah |last2=Wanlass |first2=Frank |author2-link=Frank Wanlass |date=1963 |title=Nanowatt logic using field-effect metal-oxide semiconductor triodes |conference=1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |volume=VI |pages=32–33 |doi=10.1109/ISSCC.1963.1157450}}</ref><ref>Wanlass, F., "Low stand-by power complementary field effect circuitry", {{patent|US|3356858}}, issued December 5, 1967 (filed June 18, 1963).</ref>
* [[Dynamic random-access memory]] (DRAM): DRAM was developed by [[Robert H. Dennard]] at [[IBM]] in 1967.<ref>Dennard, Robert H., "Field-effect transistor memory", {{patent|US|3387286}}, issued June 4, 1968 (filed July 14, 1967)</ref>
* [[Photoresist#Chemical amplification|Chemically amplified photoresist]]: Invented by Hiroshi Ito, [[C. Grant Willson]] and J. M. J. Fréchet at IBM ''circa'' 1980,<ref>{{US patent|4491628}}, "Positive and Negative Working Resist Compositions with Acid-Generating Photoinitiator and Polymer with Acid-Labile Groups Pendant From Polymer Backbone" J. M. J. Fréchet, H. Ito and C. G. Willson 1985.[http://patft.uspto.gov/netacgi/nph-Parser?Sect2=PTO1&Sect2=HITOFF&p=1&u=%2Fnetahtml%2Fsearch-bool.html&r=1&f=G&l=50&d=PALL&RefSrch=yes&Query=PN%2F4491628], {{Webarchive|url=https://web.archive.org/web/20190202041857/http://patft.uspto.gov/netacgi/nph-Parser?Sect2=PTO1&Sect2=HITOFF&p=1&u=%2Fnetahtml%2Fsearch-bool.html&r=1&f=G&l=50&d=PALL&RefSrch=yes&Query=PN%2F4491628|date=February 2, 2019}}.</ref><ref name=Ito01>{{cite journal| last1 = Ito | first1 = H. | last2 = Willson | first2 = C. G. |journal=Polymer Engineering & Science |volume=23|issue=18|page=204|year=1983|title=Chemical amplification in the design of dry developing resist material | doi = 10.1002/pen.760231807 }}</ref><ref name=Ito02>{{cite journal| last1 = Ito | first1 = Hiroshi | first2 = C. Grant | last2 = Willson | first3 = Jean H. J. | last3 = Frechet |journal= VLSI Technology, 1982. Digest of Technical Papers. Symposium on |year=1982 |title=New UV resists with negative or positive tone }}</ref> which was 5–10 times more sensitive to ultraviolet light.<ref name="Brock">{{cite news |url=https://www.sciencehistory.org/distillations/magazine/patterning-the-world-the-rise-of-chemically-amplified-photoresists |title=Patterning the World: The Rise of Chemically Amplified Photoresists |work=Chemical Heritage Magazine|publisher=[[Chemical Heritage Foundation]] |date=2007-10-01 |first= David C. |last=Brock|access-date=27 March 2018 }}</ref> IBM introduced chemically amplified photoresist for DRAM production in the mid-1980s.<ref>{{cite journal |last1=Lamola |first1=A. A. |last2=Szmanda |first2=C. R. |last3=Thackeray |first3=J. W. |date=August 1991 |title=Chemically amplified resists |url=http://go.galegroup.com/ps/anonymous?p=AONE&sw=w&issn=0038111X&v=2.1&it=r&id=GALE%7CA11137024&sid=googleScholar&linkaccess=fulltext&authCount=1&isAnonymousEntry=true |journal=Solid State Technology |volume=34 |issue=8 |access-date=2017-11-01}}</ref><ref>{{cite web|url=http://researcher.watson.ibm.com/researcher/files/us-saswans/05389371.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://researcher.watson.ibm.com/researcher/files/us-saswans/05389371.pdf |archive-date=2022-10-09 |url-status=live |title=Chemical amplification resists: History and development within IBM |publisher=[[IBM Journal of Research and Development]] |first=Hiroshi |last=Ito  |year=2000 |access-date=2014-05-20}}</ref>
* Deep UV excimer laser [[photolithography]]: Invented by Kanti Jain<ref name="Jain_Willson">{{US patent reference|number=US 4458994 A|y=1984|m=07|d=10|inventor=Kantilal Jain, Carlton G. Willson|title=High resolution optical lithography method and apparatus having excimer laser light source and stimulated Raman shifting}}.</ref> at IBM ''circa'' 1980.<ref name=ieee1982>{{cite journal |last1=Jain |first1=K. |last2=Willson |first2=C. G. |last3=Lin |first3=B. J. |title=Ultrafast deep-UV lithography with excimer lasers |journal=IEEE Electron Device Letters |volume=3 |issue=3 |date=1982 |pages=53–55 |url=https://ieeexplore.ieee.org/document/1482581 |doi=10.1109/EDL.1982.25476|bibcode=1982IEDL....3...53J |s2cid=43335574 }}</ref><ref name="spie1990">{{cite book |last=Jain |first=K. |url=https://spie.org/Publications/Book/2301 |title=Excimer Laser Lithography |date=1990 |publisher=SPIE Press |isbn=978-0-8194-0271-4 |location=Bellingham, Washington |oclc=20492182}}</ref><ref name=LaFontaine>{{cite web |last=La Fontaine |first=Bruno |title=Lasers and Moore's Law |work=SPIE Professional |date=October 2010 |page=20 |url=http://spie.org/x42152.xml}}</ref> Prior to this, [[excimer laser]]s had been mainly used as research devices since their development in the 1970s.<ref>Basov, N. G. et al., Zh. Eksp. Fiz. i Tekh. Pis'ma. Red. 12, 473 (1970).</ref><ref>{{cite journal | last1 = Burnham | first1 = R. | last2 = Djeu | first2 = N. | year = 1976 | title =  Ultraviolet-preionized discharge-pumped lasers in XeF, KrF, and ArF| doi = 10.1063/1.88934 | journal = Appl. Phys. Lett. | volume = 29 | issue = 11| page = 707 | bibcode = 1976ApPhL..29..707B }}</ref> From a broader scientific perspective, the invention of excimer laser lithography has been highlighted as one of the major milestones in the 50-year history of the laser.<ref>{{citation|title=Lasers in Our Lives / 50 Years of Impact|url=http://www.stfc.ac.uk/Resources/PDF/Lasers50_final1.pdf|publisher=U.K. Engineering and Physical Sciences Research Council|access-date=2011-08-22|url-status=dead|archive-url=https://web.archive.org/web/20110913160302/http://www.stfc.ac.uk/Resources/PDF/Lasers50_final1.pdf|archive-date=2011-09-13}}</ref><ref>{{cite web |publisher=SPIE |title=50 Years Advancing the Laser |url=http://spie.org/Documents/AboutSPIE/SPIE%20Laser%20Luminaries.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://spie.org/Documents/AboutSPIE/SPIE%20Laser%20Luminaries.pdf |archive-date=2022-10-09 |url-status=live |access-date=2011-08-22}}</ref>
* [[Semiconductor fabrication#Back-end-of-line (BEOL) processing|Interconnect]] innovations: Interconnect innovations of the late 1990s, including chemical-mechanical polishing or [[chemical mechanical planarization]] (CMP), trench isolation, and copper interconnects—although not directly a factor in creating smaller transistors—have enabled improved [[Wafer (electronics)|wafer]] yield, additional [[Technology node#Interconnect|layers of metal]] wires, closer spacing of devices, and lower electrical resistance.<ref name="Moore_2003">{{cite conference |last=Moore |first=Gordon E.|author-link=Gordon Moore |title=transcription of Gordon Moore's Plenary Address at ISSCC 50th Anniversary |url=http://isscc.org/doc/50th/Moore_Transcript.pdf |book-title=transcription "Moore on Moore: no Exponential is forever" |conference=2003 IEEE International Solid-State Circuits Conference |conference-url=http://isscc.org/ |publisher=ISSCC |place=San Francisco, California |date=2003-02-10 |archive-url=https://web.archive.org/web/20100331010101/http://isscc.org/doc/50th/Moore_Transcript.pdf|url-status=dead |archive-date=2010-03-31 }}</ref><ref name="Steigerwald">{{cite book | doi = 10.1109/IEDM.2008.4796607| chapter = Chemical mechanical polish: The enabling technology| title = 2008 IEEE International Electron Devices Meeting| pages = 1–4| year = 2008| last1 = Steigerwald | first1 = J. M. | isbn = 978-1-4244-2377-4| s2cid = 8266949}} "Table1: 1990 enabling multilevel metallization; 1995 enabling STI compact isolation, polysilicon patterning and yield / defect reduction"</ref><ref>{{cite web |url=http://www-03.ibm.com/ibm/history/ibm100/us/en/icons/copperchip/ |archive-url=https://web.archive.org/web/20120403013037/http://www-03.ibm.com/ibm/history/ibm100/us/en/icons/copperchip/ |url-status=dead |archive-date=April 3, 2012 |title=IBM100 – Copper Interconnects: The Evolution of Microprocessors |access-date=October 17, 2012|date=2012-03-07 }}</ref>

Computer industry technology road maps predicted in 2001 that Moore's law would continue for several generations of semiconductor chips.<ref name="International Technology Roadmap">{{cite web |url=http://public.itrs.net/ |title=International Technology Roadmap for Semiconductors |access-date=2011-08-22 |url-status=dead |archive-url=https://web.archive.org/web/20110825075240/http://public.itrs.net/ |archive-date=2011-08-25 }}</ref>

=== Recent trends ===
{{Prose|section|date=March 2025}}
[[File:Threshold formation nowatermark.gif|thumb|upright=2|A simulation of electron density as gate voltage (Vg) varies in a [[nanowire]] MOSFET. The threshold voltage is around 0.45&nbsp;V. Nanowire MOSFETs lie toward the end of the ITRS road map for scaling devices below 10&nbsp;nm gate lengths.|alt=animated plot showing electron density and current as gate voltage varies ]]

One of the key technical challenges of engineering future [[Nanoelectronics|nanoscale]] transistors is the design of gates. As device dimensions shrink, controlling the current flow in the thin channel becomes more difficult. Modern nanoscale transistors typically take the form of [[multi-gate MOSFET]]s, with the [[FinFET]] being the most common nanoscale transistor. The FinFET has gate dielectric on three sides of the channel. In comparison, the [[gate-all-around]] MOSFET ([[GAAFET]]) structure has even better gate control.

* A [[gate-all-around]] MOSFET (GAAFET) was first demonstrated in 1988, by a [[Toshiba]] research team led by [[Fujio Masuoka]], who demonstrated a vertical nanowire GAAFET that he called a surrounding gate transistor (SGT).<ref>{{cite book |last1=Masuoka |first1=Fujio |author1-link=Fujio Masuoka |last2=Takato |first2=H. |last3=Sunouchi |first3=K. |last4=Okabe |first4=N. |last5=Nitayama |first5=A. |last6=Hieda |first6=K. |last7=Horiguchi |first7=F. |title=Technical Digest., International Electron Devices Meeting |chapter=High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs |date=December 1988 |pages=222–225 |doi=10.1109/IEDM.1988.32796|s2cid=114148274 }}</ref><ref>{{cite book |last1=Brozek |first1=Tomasz |title=Micro- and Nanoelectronics: Emerging Device Challenges and Solutions |date=2017 |publisher=[[CRC Press]] |isbn=9781351831345 |page=117 |url=https://books.google.com/books?id=dAhEDwAAQBAJ&pg=PA117}}</ref> Masuoka, best known as the inventor of [[flash memory]], later left Toshiba and founded Unisantis Electronics in 2004 to research surrounding-gate technology along with [[Tohoku University]].<ref>{{cite web |title=Company Profile |url=http://www.unisantis-el.jp/profile.htm |website=Unisantis Electronics |archive-url=https://web.archive.org/web/20070222112935/http://www.unisantis-el.jp/profile.htm |archive-date=22 February 2007 |access-date=17 July 2019 |url-status=dead }}</ref>
* In 2006, a team of Korean researchers from the [[Korea Advanced Institute of Science and Technology]] (KAIST) and the National Nano Fab Center developed a [[3&nbsp;nm]] transistor, the world's smallest [[nanoelectronic]] device at the time, based on FinFET technology.<ref>{{citation |url=http://www.highbeam.com/doc/1G1-145838158.html|archive-url=https://web.archive.org/web/20121106011401/http://www.highbeam.com/doc/1G1-145838158.html|url-status=dead|archive-date=6 November 2012|title=Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )|date=1 April 2006|work = Nanoparticle News }}</ref><ref>{{cite book|first=Hyunjin |last=Lee |title=2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers |chapter=Sub-5nm All-Around Gate FinFET for Ultimate Scaling |year=2006 |pages=58–59 |doi=10.1109/VLSIT.2006.1705215 |display-authors=etal|isbn=978-1-4244-0005-8 |hdl=10203/698 |s2cid=26482358 |hdl-access=free }}</ref>
* In 2010, researchers at the [[Tyndall National Institute]] in Cork, Ireland announced a junctionless transistor. A control gate wrapped around a silicon nanowire can control the passage of electrons without the use of junctions or doping. They claim these may be produced at 10&nbsp;nm scale using existing fabrication techniques.<ref>{{cite magazine |url=https://spectrum.ieee.org/junctionless-transistor-fabricated-from-nanowires| title =Junctionless Transistor Fabricated from Nanowires|date=2010-02-22|  first = Dexter | last = Johnson|magazine=IEEE Spectrum| access-date = 2010-04-20}}</ref>
* In 2011, researchers at the University of Pittsburgh announced the development of a single-electron transistor, 1.5&nbsp;nm in diameter, made out of oxide-based materials. Three wires converge on a central island that can house one or two electrons. Electrons tunnel from one wire to another through the island. Conditions on the third wire result in distinct conductive properties including the ability of the transistor to act as a solid-state memory.<ref>{{cite journal |url=http://www.sciencedaily.com/releases/2011/04/110418135541.htm |title=Super-small transistor created: Artificial atom powered by single electron |doi=10.1038/nnano.2011.56 |pmid=21499252 |date=2011-04-19 |access-date=2011-08-22|bibcode = 2011NatNa...6..343C |volume=6 |issue=6 |journal=Nature Nanotechnology |pages=343–347|last1=Cheng |first1=Guanglei |last2=Siles |first2=Pablo F. |last3=Bi |first3=Feng |last4=Cen |first4=Cheng |last5=Bogorin |first5=Daniela F. |last6=Bark |first6=Chung Wung |last7=Folkman |first7=Chad M. |last8=Park |first8=Jae-Wan |last9=Eom |first9=Chang-Beom |last10=Medeiros-Ribeiro |first10=Gilberto |last11=Levy |first11=Jeremy }}</ref> Nanowire transistors could spur the creation of microscopic computers.<ref>{{cite book|page=173|title=Physics of the Future|first=Michio | last=Kaku |author-link=Michio Kaku |publisher=Doubleday|date=2010|isbn=978-0-385-53080-4}}</ref><ref>{{cite journal |last=Yirka |first=Bob |date=2013-05-02 |title=New nanowire transistors may help keep Moore's Law alive |url=http://phys.org/news/2013-05-nanowire-transistors-law-alive.html |journal=Nanoscale |volume=5 |issue=6 |pages=2437–2441 |bibcode=2013Nanos...5.2437L |doi=10.1039/C3NR33738C |pmid=23403487 |access-date=2013-08-08}}</ref><ref>{{cite magazine|url=https://www.forbes.com/2007/06/05/nanotech-geim-graphene-pf-guru-in_jw_0605adviserqa_inl.html |title=Rejuvenating Moore's Law With Nanotechnology |magazine=Forbes |date=2007-06-05 |access-date=2013-08-08}}</ref>
* In 2012, a research team at the [[University of New South Wales]] announced the development of the first working transistor consisting of a single atom placed precisely in a silicon crystal (not just picked from a large sample of random transistors).<ref>{{cite journal |last1=Fuechsle |first1=M. |last2=Miwa |first2=J. A. |last3=Mahapatra |first3=S. |last4=Ryu |first4=H. |last5=Lee |first5=S. |last6=Warschkow |first6=O. |last7=Hollenberg |first7=L. C. |last8=Klimeck |first8=G. |last9=Simmons |first9=M. Y. |date=2011-12-16 |title=A single-atom transistor |journal=Nat Nanotechnol |volume=7 |issue=4 |pages=242–246 |bibcode=2012NatNa...7..242F |doi=10.1038/nnano.2012.21 |pmid=22343383 |s2cid=14952278}}</ref> Moore's law predicted this milestone to be reached for ICs in the lab by 2020.
* In 2015, IBM demonstrated [[7&nbsp;nm]] node chips with [[silicon–germanium]] transistors produced using EUVL. The company believed this transistor density would be four times that of the then-current [[14&nbsp;nm]] chips.<ref>{{cite news | url=https://www.wsj.com/articles/ibm-reports-advances-in-shrinking-future-chips-1436414814 | title=IBM Reports Advance in Shrinking Chip Circuitry | work=The Wall Street Journal | date=July 9, 2015 | access-date=July 9, 2015}}</ref>
* Samsung and TSMC plan to manufacture 3{{nbsp}}nm GAAFET nodes by 2021{{ndash}}2022.<ref>{{citation| url  =https://www.tomshardware.com/news/samsung-3nm-gaafet-production-2021,38426.html | title = Samsung Plans Mass Production of 3nm GAAFET Chips in 2021 | first = Lucian |last = Armasu | date = 11 January 2019| work = www.tomshardware.com }}</ref><ref>{{citation| url = https://www.eetimes.com/document.asp?doc_id=1332388 | title = TSMC Aims to Build World's First 3-nm Fab| first= Alan | last= Patterson | date= October 2, 2017 | work = www.eetimes.com }}</ref> Note that node names, such as 3{{nbsp}}nm, have no relation to the physical size of device elements (transistors).
* A [[Toshiba]] research team including T. Imoto, M. Matsui and C. Takubo developed a ''system block module'' wafer bonding process for manufacturing [[three-dimensional integrated circuit]] (3D IC) packages in 2001.<ref>{{cite book |last1=Garrou |first1=Philip |title=Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits |date=6 August 2008 |publisher=[[Wiley-VCH]] |isbn=9783527623051 |chapter=Introduction to 3D Integration |doi=10.1002/9783527623051.ch1 |pages=4 |chapter-url=https://application.wiley-vch.de/books/sample/3527332650_c01.pdf |archive-url=https://ghostarchive.org/archive/20221009/https://application.wiley-vch.de/books/sample/3527332650_c01.pdf |archive-date=2022-10-09 |url-status=live}}</ref><ref>{{cite journal |last1=Imoto |first1=T. |last2=Matsui |first2=M. |last3=Takubo |first3=C. |last4=Akejima |first4=S. |last5=Kariya |first5=T. |last6=Nishikawa |first6=T. |last7=Enomoto |first7=R. |date=2001 |title=Development of 3-Dimensional Module Package, "System Block Module" |url=https://www.tib.eu/en/search/id/BLCP%3ACN039662991/Development-of-3-Dimensional-Module-Package-System/ |journal=Electronic Components and Technology Conference |publisher=[[Institute of Electrical and Electronics Engineers]] |issue=51 |pages=552–557}}</ref> In April 2007, Toshiba introduced an eight-layer 3D IC, the 16{{nbsp}}[[Gigabyte|GB]] THGAM [[Embedded system|embedded]] [[NAND flash]] memory chip that was manufactured with eight stacked 2{{nbsp}}GB NAND flash chips.<ref>{{cite news |title=TOSHIBA COMMERCIALIZES INDUSTRY'S HIGHEST CAPACITY EMBEDDED NAND FLASH MEMORY FOR MOBILE CONSUMER PRODUCTS |url=http://www.toshiba.com/taec/news/press_releases/2007/memy_07_470.jsp |archive-url=https://web.archive.org/web/20101123023805/http://www.toshiba.com/taec/news/press_releases/2007/memy_07_470.jsp |url-status=dead |archive-date=November 23, 2010 |access-date=23 November 2010 |work=Toshiba |date=April 17, 2007}}</ref> In September 2007, [[Hynix]] introduced 24-layer 3D IC, a 16{{nbsp}}GB flash memory chip that was manufactured with 24 stacked NAND flash chips using a wafer bonding process.<ref>{{cite news |title=Hynix Surprises NAND Chip Industry |url=https://www.koreatimes.co.kr/www/news/biz/2007/09/123_9628.html |access-date=8 July 2019 |work=[[Korea Times]] |date=5 September 2007}}</ref>
* [[V-NAND]], also known as 3D NAND, allows flash memory cells to be stacked vertically using [[charge trap flash]] technology originally presented by John Szedon in 1967, significantly increasing the number of transistors on a flash memory chip. 3D NAND was first announced by Toshiba in 2007.<ref>{{cite news |title=Toshiba announces new "3D" NAND flash technology |url=https://www.engadget.com/2007/06/12/toshiba-announces-new-3d-nand-flash-technology/ |access-date=10 July 2019 |work=[[Engadget]] |date=2007-06-12}}</ref> V-NAND was first commercially manufactured by [[Samsung Electronics]] in 2013.<ref>{{cite web|url=https://www.samsung.com/semiconductor/insights/news-events/samsung-introduces-worlds-first-3d-v-nand-based-ssd-for-enterprise-applications/|title=Samsung Introduces World's First 3D V-NAND Based SSD for Enterprise Applications &#124; Samsung &#124; Samsung Semiconductor Global Website|website=www.samsung.com}}</ref><ref>{{cite web|url=https://www.eetimes.com/author.asp?section_id=36&doc_id=1319167|title=Samsung Confirms 24 Layers in 3D NAND|first=Peter|last=Clarke|website=EETimes}}</ref><ref>{{cite web|url=https://news.samsung.com/global/samsung-electronics-starts-mass-production-of-industry-first-3-bit-3d-v-nand-flash-memory|title=Samsung Electronics Starts Mass Production of Industry First 3-bit 3D V-NAND Flash Memory|website=news.samsung.com}}</ref>
* In 2008, researchers at HP Labs announced a working [[memristor]], a fourth basic passive circuit element whose existence only had been theorized previously. The memristor's unique properties permit the creation of smaller and better-performing electronic devices.<ref name="Williams08">
{{cite journal
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* In 2014, bioengineers at [[Stanford University]] developed a circuit modeled on the human brain. [[Neurogrid|Sixteen Neurocore chips]] simulate one million neurons and billions of synaptic connections, claimed to be {{val|9,000}} times faster as well as more energy efficient than a typical PC.<ref>{{cite web|url=http://news.stanford.edu/pr/2014/pr-neurogrid-boahen-engineering-042814.html|title=Stanford bioengineers create circuit board modeled on the human brain – Stanford News Release|website=news.stanford.edu|date=2014-04-28|access-date=May 4, 2014|archive-date=January 22, 2019|archive-url=https://web.archive.org/web/20190122182434/https://news.stanford.edu/pr/2014/pr-neurogrid-boahen-engineering-042814.html|url-status=dead}}</ref>
* In 2015, Intel and [[Micron Technology|Micron]] announced [[3D XPoint]], a [[non-volatile memory]] claimed to be significantly faster with similar density compared to NAND. Production scheduled to begin in 2016 was delayed until the second half of 2017.<ref>{{cite news|url=https://www.bbc.com/news/technology-33675734|title=3D Xpoint memory: Faster-than-flash storage unveiled|newspaper=BBC News|date=2015-07-28|last1=Kelion|first1=Leo}}</ref><ref>{{cite magazine|url=https://www.wired.com/2015/07/3d-xpoint/|title=Intel's New Memory Chips Are Faster, Store Way More Data|date=July 28, 2015|magazine=WIRED}}</ref><ref>{{cite news |author=Bright |first=Peter |date=March 19, 2017 |title=Intel's first Optane SSD: 375GB that you can also use as RAM |url=https://arstechnica.com/information-technology/2017/03/intels-first-optane-ssd-375gb-that-you-can-also-use-as-ram/ |access-date=March 31, 2017 |work=Ars Technica}}</ref>
* In 2017, Samsung combined its V-NAND technology with [[eUFS]] 3D IC stacking to produce a 512{{nbsp}}GB flash memory chip, with eight stacked 64-layer V-NAND dies.<ref name="anandtech-samsung-2017">{{cite news|url=https://www.anandtech.com/show/12120/samsung-starts-production-of-512-gb-ufs-chips|title=Samsung Starts Production of 512 GB UFS NAND Flash Memory: 64-Layer V-NAND, 860 MB/s Reads|last1=Shilov|first1=Anton|date=December 5, 2017|work=[[AnandTech]]|access-date=23 June 2019}}</ref> In 2019, Samsung produced a 1{{nbsp}}[[Terabyte|TB]] flash chip with eight stacked 96-layer V-NAND dies, along with [[quad-level cell]] (QLC) technology ([[4-bit]] per transistor),<ref name="electronicsweekly-samsung">{{cite news |last1=Manners |first1=David |title=Samsung makes 1TB flash eUFS module |url=https://www.electronicsweekly.com/news/business/samsung-makes-1tb-flash-module-2019-01/ |access-date=23 June 2019 |work=[[Electronics Weekly]] |date=30 January 2019}}</ref><ref name="anandtech-samsung-2018">{{cite news |last1=Tallis |first1=Billy |title=Samsung Shares SSD Roadmap for QLC NAND And 96-layer 3D NAND |url=https://www.anandtech.com/show/13497/samsung-shares-ssd-roadmap-for-qlc-nand-and-96layer-3d-nand |access-date=27 June 2019 |work=[[AnandTech]] |date=October 17, 2018}}</ref> equivalent to 2{{nbsp}}trillion transistors, the highest transistor count of any IC chip.
* In 2020, Samsung Electronics planned to produce the [[5&nbsp;nm]] node, using FinFET and [[Extreme ultraviolet lithography|EUV]] technology.<ref name="Samsung 5nm in 2020"/>{{Update inline|reason=Has it been produced?|date=May 2021}}
* In May 2021, IBM announced the creation of the first [[2 nm]] computer chip, with parts supposedly being smaller than human DNA.<ref>{{cite web|last=IBM|date=May 6, 2021|title=IBM Unveils World's First 2 Nanometer Chip Technology, Opening a New Frontier for Semiconductors|url=https://newsroom.ibm.com/2021-05-06-IBM-Unveils-Worlds-First-2-Nanometer-Chip-Technology,-Opening-a-New-Frontier-for-Semiconductors#assets_all|url-status=live|archive-url=https://web.archive.org/web/20210506142313/https://newsroom.ibm.com/2021-05-06-IBM-Unveils-Worlds-First-2-Nanometer-Chip-Technology,-Opening-a-New-Frontier-for-Semiconductors|archive-date=May 6, 2021|access-date=May 14, 2021}}</ref>

Microprocessor architects report that semiconductor advancement has slowed industry-wide since around 2010, below the pace predicted by Moore's law.<ref name="Turing Award Lecture 2018"/> Brian Krzanich, the former CEO of Intel, announced, "Our cadence today is closer to two and a half years than two."<ref>{{cite news | title = Intel Rechisels the Tablet on Moore's Law | first = Don | last = Clark | work = Wall Street Journal Digits Tech News and Analysis | date = July 15, 2015 | url = https://blogs.wsj.com/digits/2015/07/16/intel-rechisels-the-tablet-on-moores-law/ |quote=The last two technology transitions have signaled that our cadence today is closer to two and a half years than two |access-date=2015-07-16}}</ref> Intel stated in 2015 that improvements in MOSFET devices have slowed, starting at the [[22&nbsp;nm]] feature width around 2012, and continuing at [[14&nbsp;nm]].<ref>{{cite web|url=http://files.shareholder.com/downloads/INTC/867590276x0xS50863-16-105/50863/filing.pdf|title=INTEL CORP, FORM 10-K (Annual Report), Filed 02/12/16 for the Period Ending 12/26/15|access-date=2017-02-24|archive-url=https://web.archive.org/web/20181204023944/http://files.shareholder.com/downloads/INTC/867590276x0xS50863-16-105/50863/filing.pdf|archive-date=2018-12-04|url-status=dead}}</ref> Pat Gelsinger, Intel CEO, stated at the end of 2023 that "we're no longer in the golden era of Moore's Law, it's much, much harder now, so we're probably doubling effectively closer to every three years now, so we've definitely seen a slowing."<ref>{{cite web |url=https://www.tomshardware.com/tech-industry/semiconductors/intels-ceo-says-moores-law-is-slowing-to-a-three-year-cadence-but-its-not-dead-yet |title=Intel's CEO says Moore's Law is slowing to a three-year cadence, but it's not dead yet |last=Connatser |first=Matthew |date=24 December 2023 |website=Tom's Hardware |publisher=Future US |access-date=30 April 2024 |quote=...the CEO stated transistors now double closer to every three years, which is actually significantly behind the pace of Moore's Law, which dictated a two-year cadence.}}</ref>

The physical limits to transistor scaling have been reached due to source-to-drain leakage, limited gate metals and limited options for channel material. Other approaches are being investigated, which do not rely on physical scaling. These include the spin state of electron [[spintronics]], [[tunnel junction]]s, and advanced confinement of channel materials via nano-wire geometry.<ref>{{cite book |last1=Nikonov|first1=Dmitri E.|last2=Young|first2=Ian A.|date=2013-02-01|title=Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking|publisher=Cornell University Library|arxiv=1302.0244|bibcode=2013arXiv1302.0244N}}</ref> Spin-based logic and memory options are being developed actively in labs.<ref>{{cite journal|last1=Manipatruni|first1=Sasikanth|author1-link=Sasikanth Manipatruni|last2=Nikonov|first2=Dmitri E.|last3=Young|first3=Ian A.|year=2016|title=Material Targets for Scaling All Spin Logic|journal=Physical Review Applied|volume=5|issue=1|pages=014002|arxiv=1212.3362|bibcode=2016PhRvP...5a4002M|doi=10.1103/PhysRevApplied.5.014002|s2cid=1541400}}</ref><ref>{{cite journal|date=2010-02-28|title=Proposal for an all-spin logic device with built-in memory|journal=Nature Nanotechnology|volume=5|issue=4|pages=266–270|bibcode=2010NatNa...5..266B|doi=10.1038/nnano.2010.31|pmid=20190748|last1=Behin-Aein|first1=Behtash|last2=Datta|first2=Deepanjan|author3-link=Sayeef Salahuddin|last3=Salahuddin|first3=Sayeef|last4=Datta|first4=Supriyo|author4-link=Supriyo Datta}}</ref>

=== Alternative materials research ===
The vast majority of current transistors on ICs are composed principally of [[Doping (semiconductor)|doped]] silicon and its alloys. As silicon is fabricated into single nanometer transistors, [[short-channel effect]]s adversely changes desired material properties of silicon as a functional transistor. Below are several non-silicon substitutes in the fabrication of small nanometer transistors.

One proposed material is [[Indium gallium arsenide#Applications|indium gallium arsenide]], or InGaAs. Compared to their silicon and germanium counterparts, InGaAs transistors are more promising for future high-speed, low-power logic applications. Because of intrinsic characteristics of [[List of semiconductor materials#Compound semiconductors|III–V compound semiconductors]], quantum well and [[tunnel field-effect transistor|tunnel]] effect transistors based on InGaAs have been proposed as alternatives to more traditional MOSFET designs.
* In the early 2000s, the [[atomic layer deposition]] [[high-κ]] [[thin film|film]] and pitch [[double patterning|double-patterning]] processes were invented by [[Gurtej Singh Sandhu]] at [[Micron Technology]], extending Moore's law for planar CMOS technology to [[32 nanometer|30&nbsp;nm]] class and smaller.
* In 2009, Intel announced the development of 80&nbsp;nm InGaAs [[quantum well]] transistors. Quantum well devices contain a material sandwiched between two layers of material with a wider band gap. Despite being double the size of leading pure silicon transistors at the time, the company reported that they performed equally as well while consuming less power.<ref>{{cite book |pages=1–4 |publisher=IEEE |date=2009-12-07 |first1 = G. | last1 = Dewey |first2 = R. |last2 = Kotlyar |first3 = R. |last3 = Pillarisetty |first4 = M. |last4 = Radosavljevic |first5 = T. |last5 = Rakshit |first6 = H. |last6 = Then |first7 = R. |last7 = Chau|title=2009 IEEE International Electron Devices Meeting (IEDM) |chapter=Logic performance evaluation and transport physics of Schottky-gate III&ndash;V compound semiconductor quantum well field effect transistors for power supply voltages (V<sub>CC</sub>) ranging from 0.5v to 1.0v |doi=10.1109/IEDM.2009.5424314 |isbn=978-1-4244-5639-0 |s2cid=41734511 }}</ref>
* In 2011, researchers at Intel demonstrated 3-D [[Multigate device#Types|tri-gate]] InGaAs transistors with improved leakage characteristics compared to traditional planar designs. The company claims that their design achieved the best electrostatics of any III–V compound semiconductor transistor.<ref>{{cite book |vauthors = Radosavljevic R, etal |title=2011 International Electron Devices Meeting |chapter=Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/Gate-to-source separation |pages=33.1.1–33.1.4 |publisher=IEEE |date=2011-12-05 |doi=10.1109/IEDM.2011.6131661 |isbn=978-1-4577-0505-2 |s2cid=37889140 }}</ref> At the 2015 [[International Solid-State Circuits Conference]], Intel mentioned the use of III–V compounds based on such an architecture for their 7&nbsp;nm node.<ref>{{cite news |title=Intel at ISSCC 2015: Reaping the Benefits of 14nm and Going Beyond 10nm |publisher=Anandtech |date=2015-02-22 |access-date=2016-08-15 |url=http://www.anandtech.com/show/8991/intel-at-isscc-2015-reaping-the-benefits-of-14nm-and-going-beyond-10nm |first = Ian | last = Cutress}}</ref><ref>{{cite web |title=Intel forges ahead to 10nm, will move away from silicon at 7nm |website=Ars Technica |date=2015-02-23 |access-date=2016-08-15 |url=https://arstechnica.com/gadgets/2015/02/intel-forges-ahead-to-10nm-will-move-away-from-silicon-at-7nm/ |first = Sebastian | last = Anthony}}</ref>
* In 2011, researchers at the [[University of Texas at Austin]] developed an InGaAs tunneling field-effect transistors capable of higher operating currents than previous designs. The first III–V TFET designs were demonstrated in 2009 by a joint team from [[Cornell University]] and [[Pennsylvania State University]].<ref>{{cite news |title=InGaAs tunnel FET with ON current increased by 61% |publisher=Semiconductor Today |volume = 6 |issue = 6 |date=April{{ndash}}May 2011 |access-date=2016-08-15 |url=http://www.semiconductor-today.com/features/PDF/SemiconductorToday_AprMay2011_InGaAsFET.pdf |first = Mike |last = Cooke}}</ref><ref>{{cite journal |author=Zhao |first=Han |display-authors=etal |date=2011-02-28 |title=Improving the on-current of In0.7Ga0.3As tunneling field-effect-transistors by p++/n+ tunneling junction |journal=Applied Physics Letters |volume=98 |issue=9 |pages=093501 |bibcode=2011ApPhL..98i3501Z |doi=10.1063/1.3559607}}</ref>
* In 2012, a team in MIT's Microsystems Technology Laboratories developed a 22&nbsp;nm transistor based on InGaAs that, at the time, was the smallest non-silicon transistor ever built. The team used techniques used in silicon device fabrication and aimed for better electrical performance and a reduction to [[10 nanometer|10-nanometer]] scale.<ref>{{cite web |title=Tiny compound semiconductor transistor could challenge silicon's dominance |publisher=MIT News  |date=2012-10-12 |access-date=2016-08-15 |url=https://news.mit.edu/2012/tiny-compound-semiconductor-transistor-could-challenge-silicons-dominance-1210 |first = Helen| last = Knight}}</ref>

[[Biological computing]] research shows that biological material has superior information density and energy efficiency compared to silicon-based computing.<ref>{{cite journal |last1=Cavin |first1=R. K. |last2=Lugli |first2=P. |last3=Zhirnov |first3=V. V. |date=2012-05-01 |title=Science and Engineering Beyond Moore's Law |journal=Proceedings of the IEEE |volume=100 |issue=Special Centennial Issue |pages=1720–1749 |doi=10.1109/JPROC.2012.2190155 |doi-access=free}}</ref>

[[File:Graphene SPM.jpg|thumb|upright=0.8|[[Scanning probe microscopy]] image of graphene in its hexagonal lattice structure |alt=refer to caption]]
Various forms of [[graphene]] are being studied for [[graphene electronics]], e.g. [[graphene nanoribbon]] [[graphene transistor|transistors]] have shown promise since its appearance in publications in 2008. (Bulk graphene has a [[band gap]] of zero and thus cannot be used in transistors because of its constant conductivity, an inability to turn off. The zigzag edges of the nanoribbons introduce localized energy states in the conduction and valence bands and thus a bandgap that enables switching when fabricated as a transistor. As an example, a typical GNR of width of 10&nbsp;nm has a desirable bandgap energy of 0.4&nbsp;eV.<ref name="nature 2007"/><ref>{{cite conference |last=Schwierz |first=Frank |date=1–4 November 2011 |title=Graphene Transistors – A New Contender for Future Electronics |url=https://ieeexplore.ieee.org/document/5667602 |url-access=subscription |conference=10th IEEE International Conference 2010: Solid-State and Integrated Circuit Technology (ICSICT) |location=Shanghai |doi=10.1109/ICSICT.2010.5667602 <!--|access-date=2016-08-15-->}}</ref>) More research will need to be performed, however, on sub-50&nbsp;nm graphene layers, as its resistivity value increases and thus electron mobility decreases.<ref name="nature 2007">{{cite journal |last1=Avouris |first1=Phaedon |last2=Chen |first2=Zhihong |author2-link=Zhihong Chen |last3=Perebeinos |first3=Vasili |date=2007-09-30 |title=Carbon-based electronics |url=http://physics.oregonstate.edu/~tatej/COURSES/ph575/lib/exe/fetch.php?media=avouris_review_nnano.2007.300.pdf |journal=Nature Nanotechnology |volume=2 |issue=10 |pages=605–615 |bibcode=2007NatNa...2..605A |doi=10.1038/nnano.2007.300 |pmid=18654384 |access-date=2016-08-15}}</ref>