Editing OpenCores (section)

==The OpenCores library==
The library will consist of design elements from [[central processing unit]]s, [[memory controller]]s, [[peripheral]]s, [[motherboard]]s, and other components. Emerging [[semiconductor]] manufacturers could use the information and license designs for free.

The emphasis is on digital modules called "cores", commonly known as [[Semiconductor intellectual property core|IP Core]]s. The components are used for creating both custom [[integrated circuit]]s ([[Application-specific integrated circuit|ASICs]]) and [[Field-programmable gate array|FPGAs]].

The cores are implemented in the [[hardware description language]]s [[Verilog]], [[VHDL]] or [[SystemC]], which may be synthesized to either silicon or [[gate array]]s.

The project aims at using a common non-proprietary [[Bus (computing)|system bus]] named [[Wishbone (computer bus)|Wishbone]], and most components are nowadays adapted to this bus.

Among the components created by OpenCores contributors are:

* [[OpenRISC]] – a highly configurable [[Reduced instruction set computer|RISC]] central processing unit
* [[Amber (processor)|Amber (processor core)]] – an [[ARM architecture family|ARM]]-compatible RISC central processing unit
* A [[Zilog Z80]] clone
* [[USB|USB 2.0]] controller
* Tri [[Ethernet]] controller, 10/100/1000 Mbit
* [[Encryption]] units, for example [[Data Encryption Standard|DES]], [[Advanced Encryption Standard|AES]] and [[RSA (cryptosystem)|RSA]]
* [[HyperTransport]] Tunnel
* A [[PIC microcontrollers|PIC16F84]] core<ref>risc16f84 https://opencores.org/projects/risc16f84</ref>
* Zet – an [[x86]] compatible core<ref>zet86 https://opencores.org/projects/zet86</ref>