Editing POWER5 (section)

== POWER5+ ==

The POWER5+ is an improved iteration of the POWER5 introduced on 4 October 2005. Improvements initially were lower power consumption, due to the newer process it was fabricated in. The POWER5+ chip uses a 90&nbsp;nm fabrication process.  This resulted in the die size decrease from 389&nbsp;mm<sup>2</sup> to 243&nbsp;mm<sup>2</sup>.

Clock frequency was not increased at launch and remained between at 1.5 to 1.9&nbsp;GHz. On 14 February 2006, new versions raised the clock frequency to 2.2&nbsp;GHz and then to 2.3&nbsp;GHz on 25 July 2006.

The POWER5+ was packaged in the same packages as previous POWER5 microprocessors, but was also available in a quad-chip module (QCM) containing two POWER5+ dies and two L3 cache dies, one for each POWER5+ die. These QCM chips ran at a clock frequency of between 1.5 and 1.8&nbsp;GHz.