Editing Phase-change memory (section)

==PRAM vs. Flash==
PRAM's switching time and inherent scalability<ref name=scaling>{{cite journal|doi=10.1021/nl902777z | pmid=20041706 | volume=10 | issue=2 | title=Toward the Ultimate Limit of Phase Change in Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> | year=2010 | journal=Nano Letters | pages=414–9 | last1 = Simpson | first1 = R. E.| bibcode=2010NanoL..10..414S | s2cid=9585187 }}</ref> make it more appealing than [[flash memory]]. PRAM's temperature sensitivity is perhaps its most notable drawback, one that may require changes in the production process of manufacturers incorporating the technology.

Flash memory works by modulating charge ([[electron]]s) stored within the gate of a [[MOSFET|MOS transistor]]. The gate is constructed with a special "stack" designed to trap charges (either on a floating gate or in [[charge trap flash|insulator "traps"]]). The presence of charge within the gate shifts the transistor's [[threshold voltage]] <math>\,V_\mathrm{th}</math> higher or lower, corresponding to a change in the cell's [[bit]] state from 1 to 0 or 0 to 1. Changing the bit's state requires removing the accumulated charge, which demands a relatively large [[voltage]] to "suck" the electrons off the floating gate. This burst of voltage is provided by a [[charge pump]], which takes some time to build up power. General write times for common flash devices are on the order of 100[[Microsecond|&nbsp;μs]] (for a block of data), about 10,000 times the typical 10[[Nanosecond|&nbsp;ns]] read time for [[Static random-access memory|SRAM]] for example (for a [[byte]]).{{Citation needed|date=April 2022}}

PRAM can offer much higher performance in applications where writing quickly is important, both because the memory element can be switched more quickly, and also because single bits may be changed to either 1 or 0 without needing to first erase an entire block of cells. PRAM's high performance, thousands of times faster than conventional [[Hard disk drive|hard drives]], makes it particularly interesting in [[Non-volatile memory|nonvolatile memory]] roles that are currently performance-limited by memory access timing.

In addition, with flash, each burst of voltage across the cell causes degradation. As the size of the cells decreases, damage from programming grows worse because the voltage necessary to program the device does not scale with the lithography. Most flash devices are rated for, currently, only 5,000 writes per sector, and many [[flash controller]]s perform [[wear leveling]] to spread writes across many physical sectors.

PRAM devices also degrade with use, for different reasons than flash, but degrade much more slowly. A PRAM device may endure around 100 million write cycles.<ref name=DailyTech>{{Cite web |url=http://dailytech.com/Article.aspx?newsid=6371 |title=Intel to Sample Phase Change Memory This Year |access-date=2007-06-30 |archive-url=https://web.archive.org/web/20070323030303/http://dailytech.com/Article.aspx?newsid=6371 |archive-date=2007-03-23 |url-status=dead }}</ref> PRAM lifetime is limited by mechanisms such as degradation due to [[GeSbTe|GST]] [[thermal expansion]] during programming, metal (and other material) migration, and other mechanisms still unknown.

Flash parts can be programmed before being [[solder]]ed onto a [[Printed circuit board|board]], or even purchased pre-programmed. The contents of a PRAM, however, are lost because of the high temperatures needed to solder the device to a board (see [[reflow soldering]] or [[wave soldering]]). This was made worse by the requirement to have [[Restriction of Hazardous Substances Directive|lead-free]] manufacturing requiring higher soldering temperatures. A manufacturer using PRAM parts must provide a mechanism to program the PRAM "in-system" after it has been soldered in place.

The special gates used in flash memory "leak" charge (electrons) over time, causing corruption and loss of data. The [[Electrical resistivity and conductivity|resistivity]] of the memory element in PRAM is more stable; at the normal working temperature of 85&nbsp;°C, it is projected to retain data for 300 years.<ref>{{cite journal |last1=Pirovano |first1=A. |last2=Redaelli |first2=A. |last3=Pellizzer |first3=F. |last4=Ottogalli |first4=F. |last5=Tosi |first5=M. |last6=Ielmini |first6=D. |last7=Lacaita |first7=A.L. |last8=Bez |first8=R. |title=Reliability study of phase-change nonvolatile memories |journal=IEEE Transactions on Device and Materials Reliability |volume=4 |issue=3 |pages=422–7 |year=2004 |doi=10.1109/TDMR.2004.836724 |s2cid=22178768 }}</ref>

By carefully modulating the amount of charge stored on the gate, flash devices can store multiple (usually two) bits in each physical cell. In effect, this doubles the [[Density (computer storage)|memory density]], reducing cost. PRAM devices originally stored only a single bit in each cell, but [[Intel]]'s recent advances have removed this problem.{{Citation needed|date=April 2022}}

Because flash devices trap electrons to store information, they are susceptible to data corruption from [[radiation]], making them unsuitable for many space and military applications. PRAM exhibits higher resistance to radiation.

PRAM cell selectors can use various devices: [[diode]]s, [[Bipolar junction transistor|BJTs]] and [[MOSFET]]s. Using a diode or a BJT provides the greatest amount of [[Electric current|current]] for a given cell size. However, the concern with using a diode stems from parasitic currents to neighboring cells, as well as a higher voltage requirement, resulting in higher power consumption. [[Chalcogenide]] resistance is necessarily larger than that of a diode, meaning operating voltage must exceed 1&nbsp;V by a wide margin to guarantee adequate [[P–n junction#Forward bias|forward bias]] current from the diode. Perhaps the most severe consequence of using a diode-selected array, in particular for large arrays, is the total [[P–n junction#Reverse bias|reverse bias]] leakage current from the unselected bit lines. In [[transistor]]-selected arrays, only the selected bit lines contribute reverse bias leakage current. The difference in leakage current is several orders of magnitude. A further concern with scaling below 40&nbsp;nm is the effect of discrete [[dopant]]s as the [[P–n junction|p-n junction]] width scales down. [[Thin-film transistor|Thin film]]-based selectors allow higher densities, utilizing <&nbsp;4&nbsp;F<sup>2</sup> cell area by stacking memory layers horizontally or vertically. Often the isolation capabilities are inferior to the use of transistors if the on/off ratio for the selector is not sufficient, limiting the ability to operate very large arrays in this architecture. Chalcogenide-based threshold switches have been demonstrated as a viable selector for high-density PCM arrays <ref>{{cite book |last1=Karpov |first1=I.V. |last2=Kencke |first2=D. |last3=Kau |first3=D. |last4=Tang |first4=S. |last5=Spadini |first5=G. |chapter=Phase Change Memory with Chalcogenide Selector (PCMS): Characteristic Behaviors, Physical Models and Key Material Properties |title=Symposium G – Materials and Physics for Nonvolatile Memories II |publisher=Cambridge University Press |series=MRS Proceedings |volume=1250 |year=2010 |isbn= |pages=G14-01–H07-01 |doi=10.1557/PROC-1250-G14-01-H07-01}}</ref>