Editing Physical Address Extension (section)

== Page table structures ==

=== 32-bit paging, 4 KiB pages, without PAE ===
[[File:X86 Paging 4K.svg|400px|thumb|right|No PAE, 4&nbsp;KB pages]]
In [[protected mode]] with paging enabled (bit&nbsp;31, <code>PG</code>, of control register <code>CR0</code> is set), but without PAE, [[x86]] processors use a two-level page translation scheme. [[Control register]] <code>CR3</code> holds the page-aligned physical address of a single 4&nbsp;KB long ''page directory''. This is divided into 1024 four-byte page directory entries that in turn, if valid, hold the page-aligned physical addresses of [[page table]]s, each 4&nbsp;KB in size. These similarly consist of 1024 four-byte page table entries which, if valid, hold the page-aligned physical addresses of 4&nbsp;KB long [[page (computing)|pages]] of physical memory (RAM).

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=== 32-bit paging, 4 MiB pages, without PAE ===
[[File:X86 Paging 4M.svg|400px|thumb|right|No PAE, 4&nbsp;MB pages]]
The entries in the page directory have an additional flag in bit&nbsp;7, named <code>PS</code> (for ''page size''). If the system has set this bit to <code>1</code>, the page directory entry does not point to a page table but to a single, large 4&nbsp;MB page ([[Page Size Extension]]).

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=== 32-bit paging, 4 KiB pages, with PAE ===
[[File:X86 Paging PAE 4K.svg|400px|thumb|right|With PAE; 4&nbsp;KB pages]]

Enabling PAE (by setting bit&nbsp;5, <code>PAE</code>, of the system register <code>CR4</code>) causes major changes to this scheme. By default, the size of each page remains as 4&nbsp;KB. Each entry in the page table and page directory becomes 64&nbsp;bits long (8&nbsp;bytes), instead of 32&nbsp;bits, to allow for additional address bits. However, the size of each table ''does not'' change, so both table and directory now have only 512 entries. Because this allows only one half of the entries of the original scheme, an extra level of hierarchy has been added, so the system register {{code|CR3}} now points physically to a ''Page Directory Pointer Table'', a short table containing four pointers to page directories.

Supporting 64&nbsp;bit addresses in the page-table is a significant change as this enables two changes to the processor addressing. Firstly, the page table walker, which uses physical addresses to access the page table and directory, can now access physical addresses greater than the 32-bit physical addresses supported in systems without PAE. From {{code|CR3}}, the page table walker can access page directories and tables that are beyond the 32-bit range. Secondly, the physical address for the data being accessed (stored in the page table) can be represented as a physical address larger than the 32-bit addresses supported in a system without PAE. Again, this allows data accesses to access physical memory regions beyond the 32-bit range.<ref name="Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, Chapter 4.4 Paging">{{cite book |title=Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A |chapter=4.4 Paging |url=https://www.intel.com/content/www/us/en/content-details/782158/intel-64-and-ia-32-architectures-software-developer-s-manual-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4.html?wapkw=intel%2064%20and%20ia-32%20architectures%20software%20developer%27s%20manual&docid=782161 |publisher=[[Intel]] |access-date=28 October 2023}}</ref>

=== 32-bit paging, 2 MiB pages, with PAE ===
[[File:X86 Paging PAE 2M.svg|400px|thumb|right|With PAE; 2&nbsp;MB pages]]
The entries in the page directory have an additional flag in bit&nbsp;7, named <code>PS</code> (for ''page size''). If the system has set this bit to <code>1</code>, the page directory entry does not point to a page table but to a single, large 2&nbsp;MB page ([[Page Size Extension]]).

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=== Summary of 32-bit paging===
In all page table formats supported by [[IA-32]] and [[x86-64]], the 12 least significant bits of the page table entry are either interpreted by the memory management unit or are reserved for operating system use. In processors that implement the "no-execute" or "execution disable" feature, the most significant bit (bit&nbsp;63) is the [[NX bit]]. The next eleven most significant bits (bits 52 through 62) are reserved for operating system use by both Intel and AMD's architecture specifications. Thus, from 64 bits in the page table entry, 12 low-order and 12 high-order bits have other uses, leaving 40 bits (bits 12 though 51) for the physical page number. Combined with 12 bits of "offset within page" from the linear address, a maximum of 52&nbsp;bits are available to address physical memory. This allows a maximum RAM configuration of 2<sup>52</sup>&nbsp;bytes, or 4&nbsp;petabytes (about 4.5×10<sup>15</sup> bytes).

=== x86-64 paging ===
On [[x86-64]] processors in native [[long mode]], the address translation scheme uses PAE but adds a fourth table, the 512-entry ''page-map level&nbsp;4'' table, and extends the page directory pointer table to 512&nbsp;entries instead of the original 4&nbsp;entries it has in protected mode. This means that 48&nbsp;bits of virtual page number are translated, giving a virtual address space of up to 256&nbsp;TB.  For some processors, a mode can be enabled with a fifth table, the 512-entry [[Intel 5-level paging|page-map level&nbsp;5 table]]; this means that 57&nbsp;bits of virtual page number are translated, giving a virtual address space of up to 128&nbsp;PB.<ref name="amd-24593"/>{{rp|pages=141–153}}
In the page table entries, in the original specification, 40&nbsp;bits of physical page number are implemented.