Editing Place and route (section)

==Integrated circuits==
The IC place-and-route stage typically starts with one or more schematics, HDL files, or pre-routed [[IP core]]s, or some combination of all three. It produces an IC layout that is automatically converted to a [[mask work]] in the standard [[GDS II Stream Format|GDS II]] or the [[Open Artwork System Interchange Standard|OASIS]] format.<ref>A. Kahng, J. Lienig, I. Markov, J. Hu: "VLSI Physical Design: From Graph Partitioning to Timing Closure", Springer (2022), {{doi|10.1007/978-3-030-96415-3}}, {{ISBN|978-3-030-96414-6}}, pp. 5-10.</ref>