Editing Prefetch input queue (section)

==Instruction queue==
The processor executes a program by fetching the instructions from memory and executing them. Usually the processor execution speed is much faster than the memory access speed. Instruction queue is used to prefetch the next instructions in a separate buffer while the processor is executing the current instruction.

With a [[Instruction pipeline|four stage pipeline]], the rate at which instructions are executed can be up to four times that of sequential execution.<ref>{{cite book|last=Zaky|first=Safwat|title=Computer Organization|year=1996|publisher=McGraw-Hill|isbn=0-07-114309-2|pages=[https://archive.org/details/isbn_9780071143097/page/310 310–329]|edition=Fourth|author2=V. Carl Hamacher|author3=Zvonko G. Vranesic|url-access=registration|url=https://archive.org/details/isbn_9780071143097/page/310}}</ref>

The processor usually has two separate units for fetching the instructions and for executing the instructions.<ref>{{cite web|title=Block diagram of 8086 CPU|url=http://www.compeng.dit.ie/staff/tscarff/BIU/bus_interface_unit.htm}}</ref><ref>{{cite book|last=Hall|first=Douglas|title=Microprocessors and Interfacing|year=2006|publisher=Tata McGraw-Hill|isbn=0-07-060167-4|pages=2.12}}</ref>

The implementation of a [[Pipeline (computing)|pipeline]] architecture is possible only if the bus interface unit and the execution unit are independent. While the execution unit is decoding or executing an instruction which does not require the use of the [[System bus|data]] and [[address bus]]es, the bus interface unit fetches [[Opcode|instruction opcodes]] from the memory.

This process is much faster than sending out an address, reading the opcode and then decoding and executing it. Fetching the next instruction while the current instruction is being decoded or executed is called pipelining.<ref>{{cite book|last=Hall|first=Douglas|title=Microprocessors and Interfacing|year=2006|publisher=Tata McGraw-Hill|location=New Delhi|isbn=0-07-060167-4|pages=2.13–2.14}}</ref>

The [[Intel 8086|8086]] processor has a six-byte prefetch instruction pipeline, while the [[Intel 8088|8088]] has a four-byte prefetch. As the Execution Unit is executing the current instruction, the bus interface unit reads up to six (or four) bytes of opcodes in advance from the memory. The queue lengths were chosen based on simulation studies.<ref>{{cite journal |last1=McKevitt |first1=James |last2=Bayliss |first2=John |title=New options from big chips |journal=IEEE Spectrum |date=March 1979 |volume=16 |issue=3 |pages=28–34|doi=10.1109/MSPEC.1979.6367944 |s2cid=25154920 }}</ref>

An exception is encountered when the execution unit encounters a [[Branch (computer science)|branch]] instruction i.e. either a jump or a call instruction. In this case, the entire queue must be dumped and the contents pointed to by the instruction pointer must be fetched from memory.