Editing Processor design (section)

=== Implementation logic ===
Device types used to implement the logic include:
* Individual [[vacuum tube]]s, individual [[transistor]]s and semiconductor [[diode]]s, and [[transistor-transistor logic]] [[small-scale integration]] logic chips – no longer used for CPUs
* [[Programmable array logic]] and [[programmable logic device]]s – no longer used for CPUs
* [[Emitter-coupled logic]] (ECL) [[gate array]]s – no longer common
* [[CMOS]] [[gate array]]s – no longer used for CPUs
* [[CMOS]] [[Integrated circuit|mass-produced IC]]s – the vast majority of CPUs by volume
* [[CMOS]] [[Application-specific integrated circuit|ASIC]]s – only for a minority of special applications due to expense
* [[Field-programmable gate array]]s (FPGA) – common for [[soft microprocessor]]s, and more or less required for [[reconfigurable computing]]

A CPU design project generally has these major tasks:
* Programmer-visible [[instruction set architecture]], which can be implemented by a variety of [[microarchitecture]]s
* Architectural study and performance modeling in [[ANSI C]]/[[C++]] or [[SystemC]]{{clarify|date=January 2013}}
* [[High-level synthesis]] (HLS) or [[register transfer level]] (RTL, e.g. logic) implementation
* [[Register transfer language|RTL]] verification
* [[Circuit design]] of speed critical components (caches, registers, ALUs)
* [[Logic synthesis]] or logic-gate-level design
* [[Static timing analysis|Timing analysis]] to confirm that all logic and circuits will run at the specified operating frequency
* Physical design including [[Floorplan (microelectronics)#Floorplanning|floorplanning]], [[place and route]] of logic gates
* Checking that RTL, gate-level, transistor-level and physical-level representations are equivalent
* Checks for [[signal integrity]], [[design rule checking|chip manufacturability]]

Re-designing a CPU core to a smaller die area helps to shrink everything (a "[[photomask]] shrink"), resulting in the same number of transistors on a smaller die. It improves performance (smaller transistors switch faster), reduces power (smaller wires have less [[parasitic capacitance]]) and reduces cost (more CPUs fit on the same wafer of silicon). Releasing a CPU on the same size die, but with a smaller CPU core, keeps the cost about the same but allows higher levels of integration within one [[very-large-scale integration]] chip (additional cache, multiple CPUs or other components), improving performance and reducing overall system cost.

As with most complex electronic designs, the [[functional verification|logic verification]] effort (proving that the design does not have bugs) now dominates the project schedule of a CPU.

Key CPU architectural innovations include [[index register]], [[CPU cache|cache]], [[virtual memory]], [[instruction pipelining]], [[superscalar]], [[Complex instruction set computer|CISC]], [[Reduced instruction set computer|RISC]], [[virtual machine]], [[emulator]]s, [[microprogram]], and [[Stack (data structure)|stack]].