Editing Processor power dissipation (section)

=== Reduction ===
Power consumption can be reduced in several ways,{{cn|date=March 2019}} including the following:
* Voltage reduction{{snd}} [[dual-voltage CPU]]s, [[dynamic voltage scaling]], [[undervolting]], etc.
* Frequency reduction{{snd}} [[underclocking]], [[dynamic frequency scaling]], etc.
* Capacitance reduction{{snd}} increasingly [[integrated circuit]]s that replace PCB traces between two chips with relatively lower-capacitance on-chip metal interconnect between two sections of a single integrated chip; [[low-κ dielectric]], etc.
* [[Power gating]] techniques such as [[clock gating]] and [[globally asynchronous locally synchronous]], which can be thought of as reducing the capacitance switched on each clock tick, or can be thought of as locally reducing the clock frequency in some sections of the chip.
* Various techniques to reduce the switching activity{{snd}} number of transitions the CPU drives into off-chip data buses, such as non-multiplexed [[address bus]], [[bus encoding]] such as [[Gray code addressing]],<ref>{{cite report |first1=Ching-Long |last1=Su |first2=Chi-Ying |last2=Tsui |first3=Alvin M. |last3=Despain |url=http://www.scarpaz.com/2100-papers/Power%20Estimation/su94-low%20power%20architecture%20and%20compilation.pdf |title=Low Power Architecture Design and Compilation Techniques for High-Performance Processors |date=1994 |publisher=Advanced Computer Architecture Laboratory |id=ACAL-TR-94-01}}</ref> or [[value cache encoding]] such as power protocol.<ref>{{cite book |first1=K. |last1=Basu |first2=A. |last2=Choudhary |first3=J. |last3=Pisharath |first4=M. |last4=Kandemir |title=35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings. |chapter=Power protocol: Reducing power dissipation on off-chip data buses |url=http://cucis.eecs.northwestern.edu/publications/pdf/BasCho02A.pdf |pages=345–355 |date=2002 |doi=10.1109/MICRO.2002.1176262 |isbn=978-0-7695-1859-6 |citeseerx=10.1.1.115.9946 |s2cid=18811466 }}</ref> Sometimes an "activity factor" (''A'') is put into the above equation to reflect activity.<ref name="ActivityFactor">{{cite journal | title = Timing-aware power-optimal ordering of signals | author = K. Moiseev, A. Kolodny and S. Wimer | journal = ACM Transactions on Design Automation of Electronic Systems |volume=13 |issue=4 |date=September 2008| pages = 1–17 | doi = 10.1145/1391962.1391973 | s2cid = 18895687 }}</ref>
* Sacrificing transistor density for higher frequencies.
* Layering heat-conduction zones within the CPU framework ("Christmassing the Gate").
* Recycling at least some of that energy stored in the capacitors (rather than dissipating it as heat in transistors){{snd}} [[adiabatic circuit]], energy recovery logic, etc.
* Optimizing machine code - by implementing compiler optimizations that [[Instruction scheduling|schedules]] clusters of instructions using common components, the CPU power used to run an application can be significantly reduced.<ref>{{Cite book |last1=Al-Khatib |first1=Zaid |last2=Abdi |first2=Samar |title=Applied Reconfigurable Computing |chapter=Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA |date=2015-04-13 |volume=9040 |publisher=Springer, Cham |pages=65–76 |doi=10.1007/978-3-319-16214-0_6|series=Lecture Notes in Computer Science |isbn=978-3-319-16213-3 }}</ref>